JPS5650427A - Data transfer unit - Google Patents

Data transfer unit

Info

Publication number
JPS5650427A
JPS5650427A JP12761279A JP12761279A JPS5650427A JP S5650427 A JPS5650427 A JP S5650427A JP 12761279 A JP12761279 A JP 12761279A JP 12761279 A JP12761279 A JP 12761279A JP S5650427 A JPS5650427 A JP S5650427A
Authority
JP
Japan
Prior art keywords
circuit
error
data
buffer
status information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12761279A
Other languages
Japanese (ja)
Inventor
Akira Jitsupou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12761279A priority Critical patent/JPS5650427A/en
Publication of JPS5650427A publication Critical patent/JPS5650427A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To shorten the data transfer time for transmission to peripheral devices and reduce the hardware quantity, by transmitting all data which are read till error detection and by transmitting status information.
CONSTITUTION: When presence or absence of errors of read data from memory 2 is detected by memory error detecting circuit 5 of data transfer unit 1, error status information is generated according to the error condition. Circuit 5 reports errors to memory read request control circuit 6, and circuit 6 reports errors to buffer address circuit 7. Circuit 5 uses error flag set line 110 to set error flag bit 13 to buffer 4 and writes error status information, which should be buffer data, the error flag, and the parity, which is generated from the error flag and information, to the address of buffer 4. Succeeding data requests from one peripheral device 3-a or 3-b are suppressed by circuit 7, and data from the other device 3-b or 3-a is transferred.
COPYRIGHT: (C)1981,JPO&Japio
JP12761279A 1979-10-02 1979-10-02 Data transfer unit Pending JPS5650427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12761279A JPS5650427A (en) 1979-10-02 1979-10-02 Data transfer unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12761279A JPS5650427A (en) 1979-10-02 1979-10-02 Data transfer unit

Publications (1)

Publication Number Publication Date
JPS5650427A true JPS5650427A (en) 1981-05-07

Family

ID=14964388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12761279A Pending JPS5650427A (en) 1979-10-02 1979-10-02 Data transfer unit

Country Status (1)

Country Link
JP (1) JPS5650427A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58189717A (en) * 1982-04-30 1983-11-05 Hitachi Ltd Interlocking system of data exchange

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58189717A (en) * 1982-04-30 1983-11-05 Hitachi Ltd Interlocking system of data exchange
JPS6245573B2 (en) * 1982-04-30 1987-09-28 Hitachi Ltd

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