JPS5597079A - Memory device for address conversion - Google Patents

Memory device for address conversion

Info

Publication number
JPS5597079A
JPS5597079A JP361579A JP361579A JPS5597079A JP S5597079 A JPS5597079 A JP S5597079A JP 361579 A JP361579 A JP 361579A JP 361579 A JP361579 A JP 361579A JP S5597079 A JPS5597079 A JP S5597079A
Authority
JP
Japan
Prior art keywords
circuit
address
original state
data
address conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP361579A
Other languages
Japanese (ja)
Inventor
Shozo Nagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP361579A priority Critical patent/JPS5597079A/en
Publication of JPS5597079A publication Critical patent/JPS5597079A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To secure the highly effective detection for the defect of the hardware by writing the prescribed information into the address conversion memory circuit before starting the system operation. CONSTITUTION:Address generation circuit 2 which is necessary to write the data decided at the original state is connected to the address reception part via selector 6. Thus the address information can be received in switching from the CPU. At the same time, data control circuit 23 is connected to the data reception part, and thus the writing data decided at the original state can be given to address conversion memory circuit 25. Accordingly, the access can be given to all addresses from circuit 2 after receiving the original state signal. And the fixed writing data featuring the correct parity bit and generated from circuit 23 can be written. In such way, the error occurrence other than the hardware defect is eliminated, thus ensuring the highly effective detection for the hardware defect.
JP361579A 1979-01-16 1979-01-16 Memory device for address conversion Pending JPS5597079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP361579A JPS5597079A (en) 1979-01-16 1979-01-16 Memory device for address conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP361579A JPS5597079A (en) 1979-01-16 1979-01-16 Memory device for address conversion

Publications (1)

Publication Number Publication Date
JPS5597079A true JPS5597079A (en) 1980-07-23

Family

ID=11562389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP361579A Pending JPS5597079A (en) 1979-01-16 1979-01-16 Memory device for address conversion

Country Status (1)

Country Link
JP (1) JPS5597079A (en)

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