JPS5643738A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5643738A JPS5643738A JP11968379A JP11968379A JPS5643738A JP S5643738 A JPS5643738 A JP S5643738A JP 11968379 A JP11968379 A JP 11968379A JP 11968379 A JP11968379 A JP 11968379A JP S5643738 A JPS5643738 A JP S5643738A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystal
- substrate
- type
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To readily isolate a first and the second layers by a method wherein an other conductive type first layer and an insulator are selectively formed on one conductive substrate, the other conductive 2nd layer is grown wholly to form a monocrystal on the first layer, the polycrystal on the insulator, and oxidize the polycrystal. CONSTITUTION:After an N type buried layer 21 is selectively formed on a P type Si substrate 20 selectively, an SiO2 layer is formed among the bruied layer so as to project from the surface of the substrate. Next thereto, An N type opitaxial growth is made on a whole surface to form the monocrystal layer 24a-24c on the exposed substrate, the polycrystal layer 25 on an SiO2 layer 23, after the said polycrystal layer 25 is etched in the required quantity, it is oxidized to convert to the SiO2 layer 29 connecting with the SiO2 layer 23. In this way, the N<+> layer and the N layer is readily isolated to realize the high pressure, the high density.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11968379A JPS5643738A (en) | 1979-09-17 | 1979-09-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11968379A JPS5643738A (en) | 1979-09-17 | 1979-09-17 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5643738A true JPS5643738A (en) | 1981-04-22 |
Family
ID=14767456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11968379A Pending JPS5643738A (en) | 1979-09-17 | 1979-09-17 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5643738A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6165919U (en) * | 1984-10-02 | 1986-05-06 |
-
1979
- 1979-09-17 JP JP11968379A patent/JPS5643738A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6165919U (en) * | 1984-10-02 | 1986-05-06 |
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