JPS56101764A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS56101764A
JPS56101764A JP473480A JP473480A JPS56101764A JP S56101764 A JPS56101764 A JP S56101764A JP 473480 A JP473480 A JP 473480A JP 473480 A JP473480 A JP 473480A JP S56101764 A JPS56101764 A JP S56101764A
Authority
JP
Japan
Prior art keywords
layer
photoresist
inconvenient
manufacture
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP473480A
Other languages
Japanese (ja)
Other versions
JPS606546B2 (en
Inventor
Yoshinobu Mutsukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55004734A priority Critical patent/JPS606546B2/en
Publication of JPS56101764A publication Critical patent/JPS56101764A/en
Publication of JPS606546B2 publication Critical patent/JPS606546B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

PURPOSE:To simplify the manufacturing process of a HYB IC by a method wherein a thin film resistor is prepared in such a way that a dumbbell part is not allowed to form on the surface to omit an inconvenient photoresist covering process. CONSTITUTION:The required part of a Ta thin film 5 on an insulated substrate 4 is electrolytically formed an anodic oxide layer 7. Next an Ni-Cr layer 8 and an Au layer 9 are formed, and a photoresist layer is made to cover the above layers in such a way that the width of central photoresist layer 10' is smaller than that of the anodic oxide layer 7. After plating the surface with Au 11 and Ni, the photoresist layers 10, 10' are removed to form a selective plated layer through lifting-off. With the plated layer as a mask, the Au layer 9 and Ni-Cu layer 8 are etched and then the exposed surface of the Ta layer 5 is removed immediately after the etching. By so doing, no dumbbell part is formed between electrodes 2, 2' and a resistive element 1, so that an inconvenient photoresist covering process can be omitted.
JP55004734A 1980-01-19 1980-01-19 Hybrid IC manufacturing method Expired JPS606546B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55004734A JPS606546B2 (en) 1980-01-19 1980-01-19 Hybrid IC manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55004734A JPS606546B2 (en) 1980-01-19 1980-01-19 Hybrid IC manufacturing method

Publications (2)

Publication Number Publication Date
JPS56101764A true JPS56101764A (en) 1981-08-14
JPS606546B2 JPS606546B2 (en) 1985-02-19

Family

ID=11592126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55004734A Expired JPS606546B2 (en) 1980-01-19 1980-01-19 Hybrid IC manufacturing method

Country Status (1)

Country Link
JP (1) JPS606546B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0175654A2 (en) * 1984-07-20 1986-03-26 SELENIA INDUSTRIE ELETTRONICHE ASSOCIATE S.p.A. Procedure for the manufacturing of double layer resistive thin film integrated resistors through ion erosion

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0175654A2 (en) * 1984-07-20 1986-03-26 SELENIA INDUSTRIE ELETTRONICHE ASSOCIATE S.p.A. Procedure for the manufacturing of double layer resistive thin film integrated resistors through ion erosion

Also Published As

Publication number Publication date
JPS606546B2 (en) 1985-02-19

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