JPS5750459A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS5750459A
JPS5750459A JP55126229A JP12622980A JPS5750459A JP S5750459 A JPS5750459 A JP S5750459A JP 55126229 A JP55126229 A JP 55126229A JP 12622980 A JP12622980 A JP 12622980A JP S5750459 A JPS5750459 A JP S5750459A
Authority
JP
Japan
Prior art keywords
resist
metallic
layer
layers
metallic layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55126229A
Other languages
Japanese (ja)
Inventor
Shigemi Tachiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55126229A priority Critical patent/JPS5750459A/en
Publication of JPS5750459A publication Critical patent/JPS5750459A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

PURPOSE:To obtain a highly accurate plating pattern, by a method wherein patterning is applied after depositing a thin conductor layer on an insulating substrate through metallic layers and a plated metallic layer is formed on the conductor layer. CONSTITUTION:A positive type resist 5 is provided on metallic layers formed by consecutively depositing the first metallic layer 2 formed as a resistor, the second metallic layer 3 to obtain close contact, and the third Au layer 4 on an insulating substrate 1. Patterning is applied to the third and the second metallic layers by using the resist 5 as a mask. With exposure development applied by adhering a negative type resist 7 on the first metallic layer 2 and the resist 5, only the resist 7 on the metallic layer 2 is left to expose Au layers 4. Plating 8 is applied on the Au layers 4. A desired gold plated conductor circuit can be obtained by removing the resist 7 and the exposed metallic layer 2. This method forms a plating pattern of high accuracy.
JP55126229A 1980-09-11 1980-09-11 Manufacture of hybrid integrated circuit Pending JPS5750459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55126229A JPS5750459A (en) 1980-09-11 1980-09-11 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55126229A JPS5750459A (en) 1980-09-11 1980-09-11 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5750459A true JPS5750459A (en) 1982-03-24

Family

ID=14929960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55126229A Pending JPS5750459A (en) 1980-09-11 1980-09-11 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5750459A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0233994A (en) * 1988-06-27 1990-02-05 American Teleph & Telegr Co <Att> Manufacture of circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0233994A (en) * 1988-06-27 1990-02-05 American Teleph & Telegr Co <Att> Manufacture of circuit

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