JPS5546586A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5546586A JPS5546586A JP12088578A JP12088578A JPS5546586A JP S5546586 A JPS5546586 A JP S5546586A JP 12088578 A JP12088578 A JP 12088578A JP 12088578 A JP12088578 A JP 12088578A JP S5546586 A JPS5546586 A JP S5546586A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead frame
- electrodes provided
- pattern
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE: To lower the cost of a semiconductor device by unifying the positions of electrodes provided on a semiconductor element and projection of lead frame to predetermined pattern.
CONSTITUTION: Copper foil 2 of predetermined thickness is adhered on a polyimide insulating film 1, and etched twice by photoetching process to thereby form first and second pattern projections 3 and 3' corresponding to the electrodes provided on the semiconductor element. A nickel lead 2' is adhered onto glass epoxy insulating substrate 1' to then provide first, second and third pattern projections 3, 3' and 3". Thus, the patterns are divided into several steps corresponding to the electrode positions of the semiconductor element in combination as required to thereby reduce the complicated lead frame economically.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12088578A JPS5546586A (en) | 1978-09-29 | 1978-09-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12088578A JPS5546586A (en) | 1978-09-29 | 1978-09-29 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5546586A true JPS5546586A (en) | 1980-04-01 |
Family
ID=14797376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12088578A Pending JPS5546586A (en) | 1978-09-29 | 1978-09-29 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5546586A (en) |
-
1978
- 1978-09-29 JP JP12088578A patent/JPS5546586A/en active Pending
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