JPS57141934A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57141934A
JPS57141934A JP56027037A JP2703781A JPS57141934A JP S57141934 A JPS57141934 A JP S57141934A JP 56027037 A JP56027037 A JP 56027037A JP 2703781 A JP2703781 A JP 2703781A JP S57141934 A JPS57141934 A JP S57141934A
Authority
JP
Japan
Prior art keywords
wiring
layer
microscopic
copper
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56027037A
Other languages
Japanese (ja)
Inventor
Yoshihiro Suzuki
Komei Yatsuno
Satoru Ogiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56027037A priority Critical patent/JPS57141934A/en
Publication of JPS57141934A publication Critical patent/JPS57141934A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To obtain a semiconductor device with a microscopic low resistant wiring by a method wherein a ceramic layer and a heat-resisting metal wiring layer are laminated alternately, a microscopic copper wiring is formed on the surface of a substrate, whereon the wiring layer was connected, and it is then connected to an element chip. CONSTITUTION:A copper film is formed at 10mum in thickness by performing plating on the surface of the multilayer ceramic substrate 2 provided on the inner layer of the conductor layer 3 whereon W-paste and the like, for example, are printed, and a microscopic conductor pattern 6 is formed by performing a photo etching. Then, the above is heat-treated in nitrogen containing a very small amount of oxygen, and after the oxide film on the surfce has been removed, a chip 4 is soldered, connected using a copper pattern 6 and a wire 7, a resin package 5 and a conductor pin 1 are provided, and the device is completed. Accordingly, a wiring pattern 6 of an excellent adhesive strength is microscopically formed and brought into a low resistive state on the surface of a ceramic substrate 2, thereby enabling to perform a high density assembling on the highly integrated chip.
JP56027037A 1981-02-27 1981-02-27 Semiconductor device Pending JPS57141934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56027037A JPS57141934A (en) 1981-02-27 1981-02-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56027037A JPS57141934A (en) 1981-02-27 1981-02-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57141934A true JPS57141934A (en) 1982-09-02

Family

ID=12209865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56027037A Pending JPS57141934A (en) 1981-02-27 1981-02-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57141934A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607752A (en) * 1983-06-27 1985-01-16 Fujitsu Ltd Semiconductor device and its manufacture
US5067007A (en) * 1988-06-13 1991-11-19 Hitachi, Ltd. Semiconductor device having leads for mounting to a surface of a printed circuit board
US5102829A (en) * 1991-07-22 1992-04-07 At&T Bell Laboratories Plastic pin grid array package
US5952716A (en) * 1997-04-16 1999-09-14 International Business Machines Corporation Pin attach structure for an electronic package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607752A (en) * 1983-06-27 1985-01-16 Fujitsu Ltd Semiconductor device and its manufacture
JPS6350865B2 (en) * 1983-06-27 1988-10-12 Fujitsu Ltd
US5067007A (en) * 1988-06-13 1991-11-19 Hitachi, Ltd. Semiconductor device having leads for mounting to a surface of a printed circuit board
US5102829A (en) * 1991-07-22 1992-04-07 At&T Bell Laboratories Plastic pin grid array package
US5952716A (en) * 1997-04-16 1999-09-14 International Business Machines Corporation Pin attach structure for an electronic package
US6438830B1 (en) 1997-04-16 2002-08-27 International Business Machines Corporation Process of producing plastic pin grid array

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