JPS56101687A - Semiconductor memory circuit - Google Patents
Semiconductor memory circuitInfo
- Publication number
- JPS56101687A JPS56101687A JP16918779A JP16918779A JPS56101687A JP S56101687 A JPS56101687 A JP S56101687A JP 16918779 A JP16918779 A JP 16918779A JP 16918779 A JP16918779 A JP 16918779A JP S56101687 A JPS56101687 A JP S56101687A
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- cell group
- gate
- assigned
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16918779A JPS56101687A (en) | 1979-12-27 | 1979-12-27 | Semiconductor memory circuit |
IE2649/80A IE52927B1 (en) | 1979-12-27 | 1980-12-16 | Semiconductor memory circuit |
EP80304529A EP0032014B1 (en) | 1979-12-27 | 1980-12-16 | Semiconductor memory circuit |
DE8080304529T DE3071990D1 (en) | 1979-12-27 | 1980-12-16 | Semiconductor memory circuit |
US06/217,803 US4393472A (en) | 1979-12-27 | 1980-12-18 | Semiconductor memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16918779A JPS56101687A (en) | 1979-12-27 | 1979-12-27 | Semiconductor memory circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56101687A true JPS56101687A (en) | 1981-08-14 |
Family
ID=15881839
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16918779A Pending JPS56101687A (en) | 1979-12-27 | 1979-12-27 | Semiconductor memory circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US4393472A (ja) |
EP (1) | EP0032014B1 (ja) |
JP (1) | JPS56101687A (ja) |
DE (1) | DE3071990D1 (ja) |
IE (1) | IE52927B1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0096359A2 (en) * | 1982-06-02 | 1983-12-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
JPH01211396A (ja) * | 1988-02-19 | 1989-08-24 | Nec Corp | デコーダバッファ回路 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4608672A (en) * | 1983-07-14 | 1986-08-26 | Honeywell Inc. | Semiconductor memory |
US4611131A (en) * | 1983-08-31 | 1986-09-09 | Texas Instruments Incorporated | Low power decoder-driver circuit |
JPS61199297A (ja) * | 1985-02-28 | 1986-09-03 | Toshiba Corp | 半導体記憶装置 |
US5237532A (en) * | 1986-06-30 | 1993-08-17 | Kabushiki Kaisha Toshiba | Serially-accessed type memory device for providing an interleaved data read operation |
JP3016392B2 (ja) * | 1987-08-28 | 2000-03-06 | 株式会社日立製作所 | スタティック型ram |
US5724540A (en) * | 1988-03-28 | 1998-03-03 | Hitachi, Ltd. | Memory system having a column address counter and a page address counter |
US5335336A (en) * | 1988-03-28 | 1994-08-02 | Hitachi, Ltd. | Memory device having refresh mode returning previous page address for resumed page mode |
JP2895488B2 (ja) * | 1988-04-18 | 1999-05-24 | 株式会社東芝 | 半導体記憶装置及び半導体記憶システム |
US5016216A (en) * | 1988-10-17 | 1991-05-14 | Waferscale Integration, Inc. | Decoder for a floating gate memory |
US5121358A (en) * | 1990-09-26 | 1992-06-09 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with power-on reset controlled latched row line repeaters |
US5128897A (en) * | 1990-09-26 | 1992-07-07 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory having improved latched repeaters for memory row line selection |
US5119340A (en) * | 1990-09-26 | 1992-06-02 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory having latched repeaters for memory row line selection |
US5388072A (en) * | 1992-04-10 | 1995-02-07 | International Business Machines Corporation | Bit line switch array for electronic computer memory |
US6246630B1 (en) | 1998-02-02 | 2001-06-12 | International Business Machines Corporation | Intra-unit column address increment system for memory |
US6002275A (en) * | 1998-02-02 | 1999-12-14 | International Business Machines Corporation | Single ended read write drive for memory |
US6038634A (en) * | 1998-02-02 | 2000-03-14 | International Business Machines Corporation | Intra-unit block addressing system for memory |
US6118726A (en) * | 1998-02-02 | 2000-09-12 | International Business Machines Corporation | Shared row decoder |
IL124863A (en) * | 1998-06-11 | 2004-05-12 | Dsp Group Ltd | Dual access memory array |
US6407961B1 (en) * | 1998-06-11 | 2002-06-18 | Dsp Group, Ltd. | Dual access memory array |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3848237A (en) * | 1973-02-20 | 1974-11-12 | Advanced Memory Syst | High speed mos random access read/write memory device |
JPS5235951A (en) * | 1975-09-16 | 1977-03-18 | Nippon Telegr & Teleph Corp <Ntt> | Memory signal detection unit |
US4074237A (en) * | 1976-03-08 | 1978-02-14 | International Business Machines Corporation | Word line clamping circuit and decoder |
JPS6023432B2 (ja) * | 1977-12-09 | 1985-06-07 | 株式会社日立製作所 | Mosメモリ |
DE2842547A1 (de) * | 1978-09-29 | 1980-04-10 | Siemens Ag | Schaltungsanordnung zum lesen und regenerieren von in ein-transistor-speicherelementen gespeicherten informationen |
US4453175A (en) * | 1979-09-19 | 1984-06-05 | Tokyo Shibaura Denki Kabushiki Kaisha | MOS Static RAM layout with polysilicon resistors over FET gates |
-
1979
- 1979-12-27 JP JP16918779A patent/JPS56101687A/ja active Pending
-
1980
- 1980-12-16 DE DE8080304529T patent/DE3071990D1/de not_active Expired
- 1980-12-16 IE IE2649/80A patent/IE52927B1/en not_active IP Right Cessation
- 1980-12-16 EP EP80304529A patent/EP0032014B1/en not_active Expired
- 1980-12-18 US US06/217,803 patent/US4393472A/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0096359A2 (en) * | 1982-06-02 | 1983-12-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
JPH01211396A (ja) * | 1988-02-19 | 1989-08-24 | Nec Corp | デコーダバッファ回路 |
Also Published As
Publication number | Publication date |
---|---|
US4393472A (en) | 1983-07-12 |
EP0032014B1 (en) | 1987-07-08 |
DE3071990D1 (en) | 1987-08-13 |
IE52927B1 (en) | 1988-04-13 |
EP0032014A3 (en) | 1983-08-24 |
IE802649L (en) | 1981-06-27 |
EP0032014A2 (en) | 1981-07-15 |
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