JPS5591156A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To eliminate the detrimental parasitic effect of a semiconductor memory having an SIT type cell configuration by providing a reverse conductivity type high density buring layer to a gate layer under the gate layer in the memory. CONSTITUTION:n<->-Type layers 26A-26C are extended selectively through n<+>-type buried layers 24A-24C, respectively on a p<->-type silicon substrate 22, and p<+>-type gate layer 28A-28C are formed via predetermined portions 26A1-26A3, respectively on the surface of the substrate 22. The n<->-type layer portions 26A1-26A3 between the portions 28A1 and 28A4 of the gate layers are channels and normally depleted. The drain portion 30a of an SiO2 film 30 on the surface of the substrate is formed thinner than the other films, and word line aluminum layers 32A-32C are disposed perpendicularly to the layers 24A-24C, respectively on the film 30 to thereby form parallel plate type information storage capacities at the respective crossovers. Since the gate layer 28A-28C do not face oppositely directly with the p<->-type layer 22 but always indirectly through the buried layers 24A-24C, respectively in this configuration, the depletion layer does not reach the layer 22 to thereby prevent in advance the undesired punch-through phenomenon.