JPS5834946B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a dynamic random access memory device comprising a transistor and a capacitor.

FIG. 1 shows a schematic structure of a conventional device of this kind.

That is, in FIG. 1, 1 is a semiconductor substrate made of p-type silicon, 2 is a field insulating film for isolation between elements, 3 is a gate insulating film, 4 is a capacitor electrode connected to a power supply 9, and 5 is a word line. 8 is a gate electrode of a transfer transistor connected to it, 6 is an n+ type diffusion region connected to a bit line 7, and 10 is a memory capacitor.

In this device configuration, 'High' or 'Lo' is transmitted through the bit line 7 and transfer gate 5.
A voltage of "w" is written to the memory capacitor 10, and conversely, the written voltage is read out from the memory capacitor 10 to the bit line 7 through the transfer gate 5.

However, in the case of such a conventional device configuration, since the capacitor, transistor, and bit line are each arranged flat on the substrate surface, a relatively large area is required, and it is necessary to improve the integration density. In order to do so, there was an inconvenience that the dimensions and shapes of each of them had to be made smaller.

In view of these conventional drawbacks, the present invention provides a dynamic random access memory device in which the integration density is improved by three-dimensionally arranging each part of the device, and the capacity thereof is also increased.

Hereinafter, one embodiment of the apparatus of the present invention will be described in detail with reference to FIG.

In the embodiment shown in FIG. 2, on a semiconductor substrate 11 made of p-type silicon, an n+ type diffusion region 13 is formed between field insulating films 12 for isolation between elements.
The + type diffusion region 13 forms a capacitor when a reverse bias is applied between it and the semiconductor substrate 11.

Further, a p-domain vapor growth layer 14 is selectively formed on the n+ type diffusion region 13, and a p-type vapor growth layer 14 is formed on the n+ type diffusion region 1
A transfer gate electrode 15 made of, for example, polycrystalline silicon is formed to be connected to the word line 18 via a gate insulating film 19 covering the sides of the p+ type vapor-phase growth 14. Form vapor growth layer 14
By forming an n+ type vapor phase epitaxy layer 16 connected to the bit line 17 thereon, a transfer transistor whose gate electrode length is determined by the thickness of the polycrystalline silicon is formed in the vertical direction.

Therefore, in the device configured in this embodiment as well, a voltage of 'High' or j to jl is written to the n+ type diffusion region 13 which becomes a memory capacitor through the bit line 17 and the transfer gate 15, and this written The voltage can be read out from the transfer gate 15 to the bit line 17.

In the above embodiment, p-type silicon was used as the semiconductor substrate, but it is not limited to this conductivity type; it is also possible to use an n-type substrate and reverse the relationship between all other n-type and p-type.
・Although the transfer gate electrode has been explained using polycrystalline silicon, it is also possible to use other conductive materials, and the gate insulating film can also be made of silicon oxide or a material with a high dielectric constant such as silicon nitride. Of course it's a good thing.

As detailed above, when using the device of the present invention, transistors and capacitors can be integrated in the vertical direction, that is, three-dimensionally, so that the integration density can be improved without reducing the size and shape of each element. In addition, it has other features such as being able to achieve large capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an outline of a dynamic random access memory device according to a conventional example, and FIG. 2 is a block diagram showing an outline of a dynamic random access memory device to which an embodiment of the present invention is applied. 11...p-type semiconductor substrate, 12...field insulating film, 13...n+ type diffusion region, 1
4...P+ type vapor phase growth layer, 15...Transfer gate electrode, 16...N+ type vapor growth layer, 17...Bit line, 18・・・・・・
・Word line, 19... Gate insulator

Claims (1)

[Claims] 1. In a dynamic semiconductor memory device whose main components are a transistor and a capacitor, the capacitor is constituted by a p-n junction between a semiconductor substrate of a first conductivity type and a diffusion region of a second conductivity type formed thereon. let me,
A semiconductor characterized in that the transistor is constituted by a vapor growth layer of a first conductivity type on the diffusion region of the second conductivity type, and a transfer gate electrode formed on the side thereof with a gate insulating film interposed therebetween. Storage device.