JPS5572079A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5572079A
JPS5572079A JP14622278A JP14622278A JPS5572079A JP S5572079 A JPS5572079 A JP S5572079A JP 14622278 A JP14622278 A JP 14622278A JP 14622278 A JP14622278 A JP 14622278A JP S5572079 A JPS5572079 A JP S5572079A
Authority
JP
Japan
Prior art keywords
type
film
substrate
region
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14622278A
Other languages
Japanese (ja)
Inventor
Katsuyuki Inayoshi
Kazutoshi Miyao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14622278A priority Critical patent/JPS5572079A/en
Publication of JPS5572079A publication Critical patent/JPS5572079A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To facilitate the concentration of low impurities and heighten the drain voltage resistance by forming a channel of the depression type element or the like using a mask layer covering the entire gate electrode of the enhancement type MIS type semiconductor element.
CONSTITUTION: A p-type Si substrate 11 is provided with a p+-type channel cut region 12 which is covered with a thick field SiO2 film 13. The surface of the substrate 11 exposed between the region and film is covered with a thin gate SiO2 film 14. Then, gate electrodes 15E and 15D each made of a polycrystaline Si are provided at the central part thereof. With the film 14 as the mask, an n-type source region 16E and drain region 17E, 16D, and 17D are individually formed by diffusion in the substrate 11. Thereafter, one electrode 15E alone of the enhancement type element is entirely covered with a photo resist 18 while ion is injected under the other electrode 15 alone whereby an n-type channel 19 is formed. An n-type impurity is injected to give a step between the regions 16E and 17E while the regions 16D and 17D are made deeper as it is.
COPYRIGHT: (C)1980,JPO&Japio
JP14622278A 1978-11-27 1978-11-27 Production of semiconductor device Pending JPS5572079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14622278A JPS5572079A (en) 1978-11-27 1978-11-27 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14622278A JPS5572079A (en) 1978-11-27 1978-11-27 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5572079A true JPS5572079A (en) 1980-05-30

Family

ID=15402863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14622278A Pending JPS5572079A (en) 1978-11-27 1978-11-27 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5572079A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4639892A (en) * 1982-11-30 1987-01-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor read-only memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4639892A (en) * 1982-11-30 1987-01-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor read-only memory device

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