JPS5565455A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5565455A
JPS5565455A JP13961078A JP13961078A JPS5565455A JP S5565455 A JPS5565455 A JP S5565455A JP 13961078 A JP13961078 A JP 13961078A JP 13961078 A JP13961078 A JP 13961078A JP S5565455 A JPS5565455 A JP S5565455A
Authority
JP
Japan
Prior art keywords
type layer
conducting
layer
type
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13961078A
Other languages
Japanese (ja)
Inventor
Isao Okura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13961078A priority Critical patent/JPS5565455A/en
Publication of JPS5565455A publication Critical patent/JPS5565455A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To lengthen information holding time and reduce current drive capacity, by providing a p-type layer via an insulating film below the conducting film of a pass gate unit, and another below the gate conducting film of the transfer gate transistor of a peripheral circuit unit on an n-type semiconductor substrate. CONSTITUTION:Conducting films 4, 4a are formed selectively on insulating films 3, 3a of n<->-type semiconductor substrate 10. After this, n-type layer 9 is formed. Next, these are covered with insulating films 5, 5a, and conducting films 6, 6a are selectively formed. Using conducting films 4-6a as mask, n<+>-type layer 8 is formed. Next, in a similar manner, p-type layer 7 is formed on n<+>-type layer 8. In this structure, the channel of the driver transistor of the peripheral circuit unit is composed of the n<->-type substrate and n<+>-type layer 8, its current drive capacity is large, and by controlling the impurity concentration, the threshold value is determined. Since n-layer 9 is provided below film 6 of the pass gate unit, the effective channel length is increased, and it is difficult for the information to disap pear. Further, by n-layer 9 below conducting film 6a of the peripheral circuit unit, the current drive capacity of the transfer gate transistor is lower than the driver, and the leakage of information is prevented.
JP13961078A 1978-11-10 1978-11-10 Manufacture of semiconductor device Pending JPS5565455A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13961078A JPS5565455A (en) 1978-11-10 1978-11-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13961078A JPS5565455A (en) 1978-11-10 1978-11-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5565455A true JPS5565455A (en) 1980-05-16

Family

ID=15249287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13961078A Pending JPS5565455A (en) 1978-11-10 1978-11-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5565455A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58100298A (en) * 1981-12-11 1983-06-14 Seiko Epson Corp Read-only memory circuit
JPS60181054U (en) * 1985-04-18 1985-12-02 富士通株式会社 semiconductor storage device
JPS61120463A (en) * 1984-11-15 1986-06-07 Mitsubishi Electric Corp Semiconductor memory device
US4891747A (en) * 1984-06-25 1990-01-02 Texas Instruments Incorporated Lightly-doped drain transistor structure in contactless DRAM cell with buried source/drain
US5196910A (en) * 1987-04-24 1993-03-23 Hitachi, Ltd. Semiconductor memory device with recessed array region
USRE38296E1 (en) * 1987-04-24 2003-11-04 Hitachi, Ltd. Semiconductor memory device with recessed array region

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58100298A (en) * 1981-12-11 1983-06-14 Seiko Epson Corp Read-only memory circuit
JPH0531239B2 (en) * 1981-12-11 1993-05-12 Seiko Epson Corp
US4891747A (en) * 1984-06-25 1990-01-02 Texas Instruments Incorporated Lightly-doped drain transistor structure in contactless DRAM cell with buried source/drain
JPS61120463A (en) * 1984-11-15 1986-06-07 Mitsubishi Electric Corp Semiconductor memory device
JPS60181054U (en) * 1985-04-18 1985-12-02 富士通株式会社 semiconductor storage device
US5196910A (en) * 1987-04-24 1993-03-23 Hitachi, Ltd. Semiconductor memory device with recessed array region
USRE38296E1 (en) * 1987-04-24 2003-11-04 Hitachi, Ltd. Semiconductor memory device with recessed array region

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