JPS58100298A - Read-only memory circuit - Google Patents

Abstract

PURPOSE:To realize a CMOSROM of high density, high speed, and low electric power consumption, by setting the threshold voltage of the FET of the cell higher than that of the FET of peripheral circuits. CONSTITUTION:When the threshold voltage VthN of MOSFETs constituting each cell of a memory cell array section 5 is lowered, the coefficient of conductivity betaN of the MOSFETs is increased. Moreover, the threshold voltage of peripheral circuits of the ROM is set to a normal value, only the threshold voltage of the cell section is lowered, and the variation of the electric current at the time of stand-by is eliminated, and thus, a high-speed ROM is realized.

Description

[Detailed description of the invention] The present invention relates to a read-only memory.

The present invention provides MO of a memory cell portion of a read-only memory.
It relates to increasing the memory access time by lowering the threshold voltage of 8FEiT.

Recent advances in LT engineering technology have been remarkable, especially in the performance of microprocessors. Computers and their applied products are becoming increasingly popular. Along with this, read-only memory (hereinafter referred to as ROM) stores control programs and various data.
High density, high speed, and low power consumption are also required.

The present invention meets such demands and easily provides a high-density, high-speed, low-power consumption ROM.

High density here refers to increasing the memory capacity without increasing the chip area, and for this purpose, the dimensions of the memory cells composed of MOEIFETs should be made as small as possible. There is a need. In addition, increasing the speed means making the access time as fast as possible (reducing it), and reducing power consumption means reducing the current during operation and the current during standby.

A typical ROM is configured as shown in FIG. When reading data at an arbitrary address, first select a predetermined row and column, detect the data in the memory cell at the intersection of the row and column, and output it via the output circuit. The time required for reading at this time (access time) is expressed by the following equation.

tacc = tR-1-tB +tc, ,,, [
1ltacC, . . . Access time tR, . . . Time until row 2 column selection 'iB. . , memory cell data detection time i0,.

,. Time from data detection to output Among this access time, the memory cell data detection time occupies a particularly large proportion. For example, relatively fast C
Even in the case of MO8 type ROM, 3-tacc = 40ONS, tR = 15ON
S, tB = 20ONS, tc3 = 5
It is about 9N8.

This memory cell data detection time tS is further
In general, when a memory cell is composed of an N-channel MO8FET, the relationship is proportional to the on-time or off-time of the ET.If the N-channel MO8FET is approximated to work in the saturation region, there is a relationship as shown in the following equation.

[F]. . , Fall time VDD, , Power supply □ Voltage βN, , Conductivity coefficient of N-channel MOEIFET VthN, . Threshold voltage C0° of N-channel MO8FET. Based on the relationship of drain capacitance (Equation 21), conventional methods have been used to increase the access time by increasing the conductivity coefficient βN of the N-channel MO8FET to reduce the memory cell data detection time.

4- Furthermore, the conductivity coefficient βN of the N-channel MO8FET is
Generally, there is a relationship as shown below.

βN=μNCQ7− * m a 131! βN. . . Electron mobility CQZ. . Gate capacitance W per unit area 0. . N
Channel width of MO8FET! ,. . Channel length of N-channel MO8FET From Equation 131, in order to increase βN, it is necessary to increase the channel width W of the MOSFET constituting the memory cell or to decrease the channel length j. Here, the method of increasing the channel width W has the disadvantage that the memory cell size is large, and therefore the chip area is small, which is disadvantageous for high density. Also, channel chief! The method of reducing the size is influenced by the pattern processing accuracy and the etching accuracy, and at the current mass production level, the minimum size is 2 μm to 3 μm, and advanced technology is required to make it even smaller. . From the above points, 5- The current pattern dimensions are minimum values and cannot be easily changed.

The present invention proposes a method for increasing speed without affecting the minimum pattern size.

Here, although the conductivity coefficient βN of the MOSFET is increased, the threshold voltage VthN is lowered to achieve higher speed.

Generally, the threshold voltage VihN is determined by the amount of impurity D to the substrate.
It depends on the amount of ORe, and when the substrate concentration is increased, the threshold voltage VtIN becomes higher and the mobility μN decreases.

Therefore, there is a relationship shown in FIG. 2 between the threshold voltage V4hN and the conductivity coefficient βN of the MOSFET.

In Figure 2, the MOS when the threshold voltage VlhN is 2■
The conductivity coefficient βN of the FET is normalized and expressed as 100. The threshold voltage V4hN is 005V is MOS
The conductivity coefficient of the FET is 175, and the threshold voltage is 2
This is an increase of 1.75 times compared to the current situation. That is, by lowering the threshold voltage ■thN, the conductivity coefficient βN of MO8F-BT increases.

Therefore, the threshold voltage VtAN should be kept as low as possible6.
Once this is done, the conductivity coefficient βN of the MOSFET increases and the access time becomes faster.

However, on the other hand, if the threshold voltage V4hN is lowered throughout the ROM circuit, there is a drawback that leakage current increases and standby current also increases. This is CM (l
This is contrary to the advantage that the standby current of SWR(]M is small. This is due to the fact that during standby,
61, +71, (7) This is because there is a large amount of current flowing into the peripheral circuits as leakage current. Therefore, if the threshold voltage V9y of the ROM peripheral circuit is set to the normal value and only the threshold voltage Vihy of the memory cell portion is lowered,
Although the current during operation increases slightly, the current during standby does not change, making it possible to create a high-speed 7ROM. CMO8 type RO
In the case of M, the operating current is several tens of amperes, and because the VthN of the memory cell portion is lowered, the current increases by about several microamperes, but the proportion of the total is small.

Note that the method of lowering VlhN only in the memory cell portion is as follows:
D08e7 to the base digit of the memory cell part (51) in FIG.
- The threshold voltage of the memory cell portion can be easily lowered because it is only necessary to change the amount, and only one glass mask is needed to select the memory cell portion. Therefore, at present, the problem with eMO8 type ROM is that the threshold voltage VthN of the entire ROM is about 0.7V, so as already mentioned, a glass mask is used to select the memory cell part. By controlling the tyranny concentration and lowering the threshold voltage of the memory cell part to 0.3 V or less, it is possible to easily achieve high density, high speed, and low power consumption without changing the ROM pattern dimensions. CMO8 type ROM can be realized.

As described above, the present invention provides a microprocessor-1 voice processor incorporating a read-only memory circuit.

It can also be applied to integrated circuits for commercial use, other applied products, and integrated circuits for composite products.

[Brief explanation of the drawing]

Figure 1: General ROM block diagram 1: Address signal 8-2: Address buffer 3: φ address column decoder 4: Address row decoder 5: Memory cell array section 6: Column selector and sense amplifier 71111 output buffer 8...output signal Figure 2...relationship between threshold voltage VilN and conduction coefficient of MOSFET. Applicant Suwa Seikosha Co., Ltd. Agent Patent Attorney Mogami 9- Figure 1 IN 1!1 Figure 2

Claims (1)

[Claims] In a read-only memory circuit composed of IllMOSF'F:T, the threshold voltage of MO8F'F:T constituting the memory cell portion of the circuit is the same as that of the memory cell of the circuit. MOS that constitutes peripheral circuits outside the section
A read-only memory circuit characterized by a low FET threshold voltage. 12) The read-only memory circuit according to claim 1, wherein the integrated circuit is constituted by a complementary MO6FET circuit. (Threshold voltage of MOSFET forming the 31 memory cell portion and MO8 forming the peripheral circuit outside the memory cell portion)
FF! 3. The read-only memory circuit according to claim 1, wherein the difference in threshold voltage of T is 0.2 V or more. −]−