JPH0531239B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a read-only memory.

The present invention relates to increasing the memory access time by lowering the threshold voltage of a MOSFET in a memory cell portion of a read-only memory.

The progress of LSI technology in recent years has been remarkable.
In particular, the performance of microprocessors has improved significantly, and high-speed, low-power CMOS devices that use low-power complementary MOSFET circuits (hereinafter referred to as CMOS)
Microcomputers and their applied products are becoming increasingly popular. In line with this, read-only memory (hereinafter referred to as ROM) that stores control programs and various data is also required to have high density, high speed, and low power consumption.

The present invention facilitates the provision of a high-density, high-speed, low-power consumption ROM based on such requirements.

High density means increasing memory capacity without increasing chip area, and to achieve this, it is necessary to reduce the dimensions of memory cells composed of MOSFETs as much as possible. In addition, high speed means to make the access time as fast (as small as possible), and low power consumption means to reduce the operating current and standby current.

A typical ROM is configured as shown in FIG. When reading data at an arbitrary address, first select a predetermined row and column, detect the data in the memory cell at the intersection of the row and column, and output it via the output circuit. The time required for reading at this time (access time) is expressed by the following equation.

tacc=t _R +t _S +t _C ...(1) tacc...Access time t _R ...Time until row and column selection t _S ...Memory cell data detection time t _C ...Time from data detection to output Within this access time In particular, the memory cell data detection time occupies a large proportion. For example, even in the case of relatively high-speed CMOS ROM,
tacc=400NS, _tR =150NS, _tS =200NS, _tC =
It is about 50NS.

This memory cell data detection time _tS is further
In general, when a memory cell is composed of an N-channel MOSFET, it is proportional to the on-time or off-time of the MOSFET.
Approximating that the MOSFET works in the saturated region, the relationship is as shown in the following equation.

t _S ∝J=2CV _DD /β _N (V _DD −Vth _N ) ² ...(2) J...Fall time V _DD ...Power supply voltage β _N ...Conductivity coefficient of N-channel MOSFET Vth _N ...N-channel MOSFET's conductivity Threshold voltage C...Drain capacitance From the relationship in equation (2), conventional methods to increase the access time are to increase the conductivity coefficient βN of the N-channel MOSFET and reduce the memory cell data detection time. It is taken.

Furthermore, the conductivity coefficient β _N of N-channel MOSFET
generally has the following relationship.

β _N = μ _N Cox picture W/l ...(3) μN...Electron mobility Cox...Gate capacitance per unit area W...Channel width of N-channel MOSFET l...Channel length of N-channel MOSFET From equation (3) , βN, it is necessary to increase the channel width W of the MOSFET constituting the memory cell or to decrease the channel length l. Here, the method of increasing the channel width W increases the memory cell size, which increases the chip area, which is disadvantageous to high density. In addition, the method of reducing the channel length l is influenced by pattern processing accuracy, especially etching accuracy, and at the current mass production level, the minimum dimension is 2 μm to 3 μm, and advanced technology is required to make it even smaller. is necessary. From the above points, the current pattern dimensions are at the minimum value and cannot be easily changed.

The present invention proposes a method for increasing speed without affecting the minimum pattern size. Here, in order to increase the conductivity coefficient β _N of the MOSFET, the threshold voltage Vth _N is lowered to achieve higher speed.

Generally, the threshold voltage Vth _N is determined by the dose of impurities in the substrate, and as the substrate concentration increases,
The threshold voltage Vth _N increases and the mobility μ _N decreases. Therefore, threshold voltage Vth _N and MOSFET
There is a relationship between the conductivity coefficient β _N and the relationship shown in FIG. In Figure 2, the threshold voltage Vth _N is 2V.
The conductivity coefficient β _N of the MOSFET is normalized and expressed as 100. When the threshold voltage Vht _N is 0.5V,
The conductivity coefficient of the MOSFET is 175, which is 1.75 times higher than when the threshold voltage is 2V. In other words, if the threshold voltage Vth _N is lowered,
The conductivity coefficient β _N of the MOSFET increases.

Therefore, if the threshold voltage VthN is kept as low as possible, the conductivity coefficient βN of the MOSFET increases and the access time becomes faster.

However, on the other hand, the threshold voltage Vth _N is
If it is lowered throughout the circuit, there is a drawback that leakage current increases and standby current also increases. This is contrary to the advantage of CMOS ROM, which has a small standby current. This is because, during standby, a large amount of current flows as a leakage current in the peripheral circuits 2, 3, 4, 6, and 7 in FIG. Therefore, the threshold voltage of the ROM peripheral circuit
If Vth _N is set to the normal value and only the threshold voltage Vth _N of the memory cell portion is lowered, the operating current will increase slightly, but the standby current will not change, resulting in a high-speed ROM. I can do it. CMOS
In the case of type ROM, the operating current is several tens of milliamperes, and by lowering the _VthN of the memory cell portion, the current increases by about several microamperes, but this is a small proportion of the total.

Note that the method of lowering Vth _N only in the memory cell portion is to attach the memory cell portion to the substrate at 5 in Figure 1.
The dose amount can be changed, and since only one glass mask is needed to select the memory cell portion, the threshold voltage of the memory cell portion can be easily lowered. Therefore, at present, in CMOS type ROM, the threshold voltage Vth _N of the entire ROM is approximately
Since it is about 0.7V, as already mentioned, use a glass mask to select the memory cell part,
By controlling the substrate concentration and lowering the threshold voltage of the memory cell part to 0.3V or less, high density, high speed, and
A CMOS type ROM with low power consumption can be realized.

As described above, the present invention can also be applied to microprocessors with built-in read-only memory circuits, integrated circuits for speech synthesis, other applied products, and integrated circuits for composite products.

[Brief explanation of the drawing]

FIG. 1...Block diagram of a general ROM, 1...address signal, 2...address buffer, 3...address column decoder, 4...address row decoder, 5...memory cell array section, 6...
Column selector and sense amplifier, 7...Output buffer, 8...Output signal, Figure 2...Relationship between threshold voltage Vth _N and conduction coefficient of MOSFET.

Claims (1)

[Scope of Claims] 1. In a memory circuit comprising a memory cell section and a peripheral circuit outside the memory cell section, a memory circuit of one conductivity type constituting the memory cell section
The MOSFET has a first threshold voltage and is a MOSFET of one conductivity type constituting the peripheral circuit.
has a second threshold voltage, and the concentration of the substrate is controlled so that the first threshold voltage is smaller than the second threshold voltage.