JPH10189883A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out high-speed operation, while reducing a leakage current at the time of a sandby mode by elevating the threshold values of first and second transistors at a potential which is supplied to first and second control electrodes for a first circuit by a third circuit during a time when a second circuit stops the supply of a clock to the first circuit. SOLUTION: A principal section is composed of a microprocessor-unit(MPU) 1 as a first circuit, a clock control circuit as a second circuit and substrate bias circuits 2-1, 2-2 as third circuits. A clock CKm fed to the MPU 1 is stopped by the clock control circuit 3 in a standby mode, while the substrate bias circuits 2-1, 2-2 are operated by an operating-mode changeover signal A, and a substrate bias VBn is applied to transistors MN, MP. The threshold values of the transistors MN, MP are elevated by applying the substrate bias VBn, and a leakage current is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption type semiconductor integrated circuit, and more particularly to an information processing apparatus such as a microprocessor which operates on a battery and uses a MOS transistor.

[0002]

2. Description of the Related Art Conventionally, as an example of a semiconductor circuit to which a substrate bias is applied, a super-high-speed MOS device published by Baifukan on Feb. 10, 1987, pp. 259 to 26
There is one described on page 1 (supervised by Takuo Sugano).

[0003] The conventional general application of a substrate bias is intended to increase the speed by reducing the pn junction capacitance as in the conventional example. On the other hand, when the substrate bias is applied, the threshold value of the n-channel MOSFET is designed to rise to a practical value of about 0.6 to 1.0 V. According to this example, as the value of the substrate bias is higher, the depletion layer of the drain is expanded, and the capacity of the pn junction is reduced, so that the speed can be increased.

On the other hand, Japanese Patent Laid-Open Publication No. Sho.
As described in Japanese Unexamined Patent Publication No. 42827/1992, there is a method in which a clock instruction to a CPU portion and a circuit that does not operate is stopped by a program instruction to enter a standby mode to reduce power consumption. In the CMOS circuit, if the clock is stopped and all switching is stopped, the power consumption is only the leakage current due to the subthreshold current of the MOS transistor, so that the current consumption in the standby mode is reduced by three digits or more compared to the operation mode. be able to.

[0005]

The current threshold value (0.
Even a microprocessor using a MOS transistor of about 5 V) can operate at high speed by using a power supply voltage of 5 V, and can operate at high speed by reducing the pn junction capacitance by applying a substrate bias as in the conventional case. there were. However, from the viewpoint of low power consumption, since power consumption is proportional to the square of the power supply voltage, it is necessary to reduce the power supply voltage to 5 V or less. In particular, in the case of battery operation, it is necessary to lower the voltage to about 1V. In addition, as the MOS transistor becomes finer, the withstand voltage of the element also decreases. Therefore, it is necessary to lower the power supply voltage.

On the other hand, the delay time of the CMOS circuit is the time for charging and discharging the charge of the load capacitance with the drain current, and is proportional to the power supply voltage / (power supply voltage-threshold) square. Therefore,
The delay time is inversely proportional to the power supply voltage at a high power supply voltage at which the threshold value can be ignored, but at a low voltage at which the threshold value cannot be ignored, the delay time sharply increases as the power supply voltage decreases. At the time of such a low-voltage operation, when the substrate bias is applied, the threshold value increases, so that there is a problem that the operation speed is rather reduced. Therefore, at the time of low-voltage operation, basically, no substrate bias is applied, and the threshold value of the MOS transistor must be kept low.

On the other hand, lowering the threshold voltage requires
Another problem occurs that the leakage current increases due to the subthreshold current of the MOS transistor. This leak current increases exponentially to about 47 times each time the threshold voltage is lowered by 0.1 V at room temperature. For example, when the threshold value is reduced from 0.5 V to 0.3 V, the leak current increases by about 2200 times. In the case of a microprocessor having a scale of several hundred thousand elements, the leakage current is 10% or less as compared with the current during operation, and the power consumption does not increase much. However, the current consumption in the standby mode in which only the clock is stopped as in the conventional example is exactly due to this leak current. Therefore, when the threshold value is lowered from 0.5 V to 0.3 V, the leak current directly increases by 2200 times. . Therefore, when the threshold voltage is lowered, merely stopping the clock does not sufficiently reduce the current consumption, and causes a problem that the battery backup time in the standby mode is significantly reduced.

The present invention has been made on the basis of the results of the study by the present inventors as described above. The purpose of the present invention is to enable high-speed operation even with a low power supply voltage during operation, and to provide a standby mode. An object of the present invention is to provide an information processing apparatus that consumes less power due to a leak current, particularly a device structure suitable for this.

[0009]

The above-mentioned problem is caused by the fact that the threshold value of the MOS transistor is low even in the standby mode in which the switching operation is not performed.

Therefore, if the threshold value is lowered during operation to enable high-speed operation even at a low power supply voltage, and if the leakage current can be reduced by increasing the threshold value in the standby mode, high-speed operation at the time of operation at a low power supply voltage is possible. And low power consumption in the standby mode. Therefore, the threshold value of the MOS transistor itself is set low, and the threshold value is raised by applying a substrate bias in the standby mode.

It is needless to say that the substrate bias at this time needs to be set so that the amount of reduction of the leak current due to the rise of the threshold value is larger than the current consumption of the substrate bias circuit.

As described above, since the leakage current cannot be stopped only by stopping the clock when the circuit is on standby, the leakage current is reduced by increasing the threshold value of the transistor by applying a substrate bias, thereby reducing the power consumption. On the other hand, when the threshold value of the transistor is changed, the operation speed of the transistor changes, so that the operation clock is controlled in conjunction with the threshold value.

Further, the present invention provides a device structure capable of easily controlling a substrate bias in a CMOS structure.

FIGS. 1 and 5 which will be described later in detail in the embodiment.
The invention of the present application shows a first region having a first conductivity type, a second region having a second conductivity type formed in the first region (see FIG. 2) having a third region (3) having a first conductivity type formed in a second region and a first region having a first conductivity type formed in a second region (2); A first transistor (PMOS) having a source / drain region and a second transistor (NMOS) having a second source / drain region having a second conductivity type formed in a third region (3). , A first circuit (1) including a first control electrode (5-2) for controlling the potential of the second region and a second control electrode (5-1) for controlling the potential of the third region. ), A second circuit (3) for supplying a clock signal to the first circuit, and a third circuit (2-1, 2-) for supplying a potential to the first and second control electrodes.
2), while the second circuit stops supplying the clock to the first circuit, the third circuit supplies the first and second control electrodes with a potential supplied to the first and second control electrodes. 2 is characterized in that the threshold value of the transistor 2 is increased.

Further, in order to enhance the controllability, a first high-concentration region (8) having a second conductivity type in which the carrier concentration formed below the channel region of the first transistor (PMOS) is higher than the surroundings. And a first transistor in which a carrier concentration formed below a channel region of the second transistor (NMOS) is higher than the surroundings.
And a second high-concentration region (7) having the above conductivity type.

The third circuit may supply at least two potentials or two potentials having different polarities.

Further, the present invention provides a substrate region having a first conductivity type, source and drain regions having a second conductivity type formed in the substrate region, and a gate disposed on a channel connecting the source and drain regions. A second circuit including a first circuit including a transistor having an electrode, a second circuit for supplying a clock signal for controlling a main circuit, and a third circuit for applying a voltage to a substrate region And the timing of voltage application by the third circuit are linked.

Alternatively, a first region having a first conductivity type and a second region having a second conductivity type formed in the first region.
Region (2), a third region (3) having a first conductivity type formed in a second region, and having a first conductivity type formed in a second region (2) A first transistor (PMOS) having a first source / drain region and a second transistor (PMOS) having a second source / drain region having a second conductivity type formed in a third region (3) NMOS), a first control electrode (5-2) for controlling the potential of the second region, a second control electrode (5-1) for controlling the potential of the third region, and a first transistor. A first high-concentration region (8) having a second conductivity type having a higher carrier concentration than the surrounding region and formed under a channel region of the second transistor (NMOS); And a second high-concentration region (7) having a first conductivity type having a higher carrier concentration than the surroundings.

[0019]

In operation, since the threshold value is low, high-speed operation is possible even at a low voltage. On the other hand, in the standby mode, the threshold voltage is high, so that the leakage current can be greatly reduced.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a typical embodiment of the present invention, and its basic concept will be described. First, in order to maintain high-speed operation at a low power supply voltage, MOS transistors (MN, MP)
Is set low. On the other hand, when there is no keyboard input for a certain period of time or when the state of the lowest power consumption continues for a certain period of time, the standby mode is entered by a program command or an external control signal.

In the standby mode, the clock control circuit 3 stops the clock Ckm supplied to the MPU (microprocessor unit) 1 and simultaneously operates the operation mode switching signal A
To operate the substrate bias circuits 2-1 and 2-2,
Negative substrate bias V is applied to the NMOS transistor (MN).
A substrate bias VBp more positive than the power supply is applied to the Bn and PMOS transistors (MP). By applying the substrate bias, the threshold value of the MOS transistor rises, and the leakage current decreases as an exponential function of the threshold rise. That is, when a substrate bias is applied, the sub-threshold characteristic is improved and the leak current is reduced. The more the microprocessor has a larger number of elements, the greater the amount of reduction in the leak current, which is equal to or greater than the current consumption of the substrate bias circuits 2-1 and 2-2. With the above operation, an information processing device that can operate at high speed at low voltage and consumes low power in the standby mode can be realized.

Next, the embodiment of FIG. 1 will be described in detail with reference to the drawings. As shown in FIG. 1, a microprocessor is configured by integrating the MPU 1, the substrate bias circuits 2-1 and 2-2, the clock control circuit 3, and the like on one chip. The MPU 1 includes an instruction fetch unit, an instruction decoder, an instruction execution unit, and the like, as is well known to those skilled in the art. MPU1 is composed of a CMOS circuit,
The threshold value of the MOS transistor is set to 0.3 V, and the threshold value of the PMOS transistor is set to -0.3 V, thereby enabling high-speed operation even when the power supply voltage Vcc is as low as 1 V. The power supply voltage Vcc of the microprocessor chip
Is connected to a battery (not shown), and the power supply voltage Vcc is supplied from the battery. In addition, terminals are provided on each of the NMOS and PMOS substrates (or well regions) of the MPU 1 to apply a substrate bias.

An operation mode switching signal A in response to a program command or an external signal is applied to substrate bias circuits 2-1 and 2-2 for NMOS and PMOS to control the levels of substrate biases VBp and VBn. Switching the mode
This can be performed under conditions such as the presence or absence of an input from a keyboard and the magnitude of current consumption. By controlling the clock control circuit 3 with the operation mode switching signal A and the frequency switching signal B, the on / off and frequency of the clock supplied to the MPU 1 are controlled.

FIG. 2 shows changes in the clock and the substrate bias in each of the normal operation mode, the low power consumption mode, and the standby mode.

In the normal operation mode, a high-speed clock of 16 MHz is supplied, and no substrate bias is applied. Accordingly, since the absolute value of the threshold value of each of the N and P channel MOS transistors remains at 0.3 V, high-speed operation is possible even with a low power supply voltage Vcc of 1 V. On the other hand, since the threshold value is low, a steady leakage current due to the subthreshold current flows. However, in the case of a 100,000 gate microprocessor, the consumption current due to the steady leakage current is 1/10 of the consumption current due to the switching operation. Since it is below, the current consumption during the operation does not change much.

In the low power consumption mode, in order to suppress power consumption due to switching, the clock control circuit 3 responds to the frequency switching signal B and sets the clock frequency to 8 MHZ divided by 2.
z. The NMOS substrate bias VBn of -0.5 V and +1.
5V PMOS substrate bias VBp is applied to
The threshold value of the S transistor is raised to about 0.5 V in absolute value. Since the operation speed is low, there is no problem in operation even if the threshold value is increased. By this low power consumption mode, the switching current can be reduced to 1/2 and the leakage current can be reduced to about 1/2200.

Since no operation is performed in the standby mode, the clock is stopped. When the clock is stopped, the switching operation stops at all. Further, in order to obtain a threshold value increased in absolute value, the substrate biases VBn and VBp are similarly calculated.
Is applied. Therefore, the current consumption of the CMOS circuit is only a leak current due to an extremely small subthreshold current corresponding to a high threshold value. Since the absolute value of the threshold is increased to about 0.5 V by applying the substrate bias,
The leak current can be suppressed to about 1/2200 of the operation.

Next, the substrate bias circuits 2-1 and 2-2
3 is shown in FIG. When the operation mode switching signal becomes 1, a clock signal is supplied to the substrate bias circuit, and the operation starts. NMOS using charge pumping circuit
And a voltage higher than the power supply voltage for the PMOS. When the power supply voltage Vcc is 1 V, bias voltages VBn and VBp of about -0.5 V for NMOS and about +1.5 V for PMOS can be generated. Since this clock signal uses a basic clock that is constantly operated for a clock, a microprocessor, and the like, a new oscillation circuit is unnecessary, and the current consumption for applying a substrate bias is 100 μm.
It is about A. In this embodiment, the substrate bias circuit is provided on the basis of a single power supply. However, in the case of battery operation, a battery dedicated to the substrate bias may be provided.

Next, an embodiment of the clock control circuit 3 is shown in FIG.
Shown in The basic clock signal is such that the operation mode switching signal A is 0
The clock output CK through the clock control circuit 3
m is supplied to the MPU 1. In the standby mode, the operation mode switching signal becomes 1, and the clock output is not supplied to MPU1. One of the clock inputs enters a frequency dividing circuit by a T flip-flop, and the other passes through to a clock frequency switching circuit. When the clock frequency switching signal B is 1, a high-speed clock is supplied to the MPU 1 as it is, and when the clock frequency switching signal B is 0, a low-speed clock for the low power consumption mode, which is divided by half, is supplied.

FIG. 5 shows an embodiment of an element structure for applying a substrate bias to a CMOS transistor. Normal C
Although it is possible to apply a bias to the MOS structure without grounding the substrate, the packaging becomes complicated,
There is a problem that noise is easily picked up. In order to apply the substrate bias VBn, VBp to the N-channel and P-channel MOS transistors with the P-type semiconductor substrate 1 grounded, the N-channel MOS substrate p-well 3 is moved from the substrate 1 to the P-channel MO.
It is insulated by the S substrate n epitaxial layer 2.
NMO is applied to the p-well 3 through the substrate bias terminal 5-1.
A negative voltage is applied to the S substrate bias VBn, and a PMOS voltage is applied to the n epitaxial layer 2 through the substrate bias terminal 5-2.
A positive voltage is applied as the substrate bias VBp, but all are insulated from each other because the bias relationship is a reverse bias of a pn junction.

Since the substrate bias voltage that can be generated at a low power supply voltage is low, the device structure is devised. P-type high concentration region 7 and P just below the gate electrode of N-channel MOS
The n-type high-concentration regions 8 immediately below the gate electrode of the channel MOS are provided at positions deeper than the thickness of the surface depletion layer when the channel inversion layer is formed. Therefore, when no substrate bias is applied, the threshold is not affected. When a substrate bias is applied, the depletion layer spreads to high concentration regions 7 and 8,
Since the effective substrate concentration is high, the threshold value greatly changes depending on the substrate bias. FIG. 6 shows changes in the substrate bias and the threshold value. The surface concentration of the p-type well 3 is 5 × 10 16
/ Cm 3, the concentration of the p-type high concentration region 7 is 3 × 10 17 /
cm3. When the p-type high-concentration region 7 is not provided, the change in the threshold value is small even when the substrate bias is applied because the substrate constant is small, and the control width of the threshold value is too small at a low power supply voltage. By providing the p-type high-concentration region 7, the substrate constant becomes twice or more and the threshold value can be largely controlled. By applying a substrate bias of 0.5 V, the threshold can be raised by about 0.2 V.

Next, as another embodiment of the present invention, FIG. 7 shows a basic configuration for automatically switching the substrate bias according to the clock frequency. A change in the frequency of the clock signal is detected by the substrate bias control circuit 2-0, and the substrate bias circuit 2-
Substrate biases VBn and VBp generated from 1 and 2-2
Switch the value of. As a result, the normal mode, the low power consumption mode, and the standby mode of the substrate bias can be switched only by the clock signal.

FIG. 8 shows an embodiment of the substrate bias control circuit 2-0. The voltage Vc is generated by the charge pump circuit from the clock signal. The value of Vc is proportional to the frequency of the clock, and can be adjusted by the coupling capacitance Cc and the load resistance Rb. When the clock frequency is high, the value of Vc is high and the MOS transistor MN1 passes through, and the signal at point a goes low, so that the ring oscillator does not oscillate and the substrate biases VBn and VBp are not applied. Next, when the clock frequency is low, since the Vc value is low and MN1 does not pass through, point a becomes high level, the ring oscillator oscillates, and the substrate bias VBn,
VBp is applied. Of course, when the clock signal stops, the point a becomes high and the substrate biases VBn, VB
p is applied. In this embodiment, since the ring oscillator is oscillated to generate the substrate bias, the power consumption in the standby mode is as large as about 300 μA, but the effect is large because the amount of reduction of the leak current is large. Further, since the substrate biases VBn and VBp automatically change according to the clock frequency, there is no need to provide a specific command or control signal.

FIG. 9 shows a change in the drain current characteristic of the MOS transistor depending on the threshold value. The leak current is a drain current when the gate voltage is 0V. As the threshold is increased from 0.3 V to 0.5 V, the leakage current drops from 44 nA to about 1/2200. Considering that a microprocessor is constituted by MOS transistors having a threshold voltage of 0.3 V and a leakage current of 44 nA, when the number of gates of the microprocessor is approximately 100,000, the leakage current is 4. Reaches 4 mA. When a substrate bias of 0.5 V is applied, the threshold value rises to 0.5 V, and the leak current decreases to about 20 pA, which is almost the same as that of a transistor whose original threshold value is 0.5 V. On the other hand, since the current consumption of the substrate bias circuit is about 100 μA, the total
A is the current consumption. FIG. 10 shows a threshold value of 0.5 V for the maximum operating frequency and current consumption of the microprocessor.
And a comparison between the conventional example of 0.3 V and this example and the present embodiment.

[0036]

According to the present invention, since the threshold voltage can be set low, high-speed operation can be performed even at a low power supply voltage. In a low-speed operation or a standby mode, the threshold voltage is increased by applying a substrate bias. Power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 shows a block diagram of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 shows waveform changes of respective portions in each mode of the semiconductor integrated circuit of FIG.

FIG. 3 shows an embodiment of a substrate bias circuit of the semiconductor integrated circuit of FIG. 1;

FIG. 4 shows an embodiment of a clock control circuit of the semiconductor integrated circuit of FIG.

FIG. 5 is a sectional view of a CMOS structure of the semiconductor integrated circuit of FIG. 1;

FIG. 6 shows a relationship between a substrate bias and a threshold voltage of a MOS transistor.

FIG. 7 shows a block diagram of a semiconductor integrated circuit according to another embodiment of the present invention.

8 shows an embodiment of the substrate bias control circuit and the substrate bias circuit of FIG.

FIG. 9 shows a relationship between an N-channel MOS transistor, a threshold voltage, and a leak current.

FIG. 10 shows a comparison between the conventional technology and the present invention with respect to the maximum operating frequency and the current consumption of the microprocessor.

[Explanation of symbols]

VBn: N-channel MOS substrate bias, VBp: P
Channel MOS substrate bias, CKm: clock signal for microprocessor, CKb: clock signal for substrate bias generation.

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 21/8238 27/092 H03K 19/094 (72) Inventor Koichi Seki 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory

Claims (6)

[Claims] A first region having a first conductivity type; a first region having a first conductivity type;
A second region having a second conductivity type formed in the region of
A third region having a first conductivity type formed in the second region and a first source / drain region having a first conductivity type formed in the second region; A first transistor, a second transistor having a second source / drain region having a second conductivity type formed in the third region, and a first transistor controlling a potential of the second region.
A first circuit including a control electrode for controlling the potential of the third region; a second circuit for supplying a clock signal to the first circuit; And a third circuit for supplying a potential to the second control electrode. While the second circuit stops supplying a clock to the first circuit, the third circuit supplies the third circuit with the third circuit. A semiconductor device, wherein the threshold values of the first and second transistors are increased by a potential supplied to first and second control electrodes. 2. A first high-concentration region formed under the channel region of the first transistor and having a second conductivity type having a higher carrier concentration than the surroundings; and a carrier formed under the channel region of the second transistor. 2. The semiconductor device according to claim 1, comprising: a second high-concentration region having a first conductivity type having a higher concentration than the surroundings. 3. The semiconductor device according to claim 1, wherein said third circuit supplies at least two potentials. 4. The semiconductor device according to claim 1, wherein said third circuit supplies two potentials having different polarities. 5. A semiconductor device comprising: a substrate region having a first conductivity type; source and drain regions having a second conductivity type formed in the substrate region; and a gate electrode disposed on a channel connecting the source and drain regions. A first circuit including a transistor having a first circuit, a second circuit for supplying a clock signal for controlling the main circuit, and a third circuit for applying a voltage to the substrate region. A semiconductor device in which timing of clock supply stop by a circuit and timing of voltage application by the third circuit are linked. 6. A first region having a first conductivity type, said first region having a first conductivity type.
A second region having a second conductivity type formed in the region of
A first region having a first conductivity type formed in the second region; a first region having a first conductivity type formed in the second region;
A first transistor having a source / drain region, and a second transistor having a second conductivity type formed in the third region.
A second transistor having a source / drain region, a first control electrode for controlling a potential of the second region, a second control electrode for controlling a potential of the third region, and the first A first high-concentration region formed under the channel region of the second transistor and having a second conductivity type having a higher carrier concentration than the surrounding region; A second high-concentration region having a higher first conductivity type.