JPS5562598A - Memory check unit - Google Patents

Memory check unit

Info

Publication number
JPS5562598A
JPS5562598A JP13429578A JP13429578A JPS5562598A JP S5562598 A JPS5562598 A JP S5562598A JP 13429578 A JP13429578 A JP 13429578A JP 13429578 A JP13429578 A JP 13429578A JP S5562598 A JPS5562598 A JP S5562598A
Authority
JP
Japan
Prior art keywords
memory
pattern
circuit
write
mut2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13429578A
Other languages
Japanese (ja)
Inventor
Atsushi Nigorikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13429578A priority Critical patent/JPS5562598A/en
Publication of JPS5562598A publication Critical patent/JPS5562598A/en
Pending legal-status Critical Current

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To facilitate a macro-analysis of a mass storage memory by storing defect information of the check result of a measured IC memory is compressed addresses of a storage part.
CONSTITUTION: Simultaneously with applying address information generated from pattern generator 1 to measured memory MuT2, corresponding address information compressed to 1/2n by address compressing multiplex circuit 4 is applied to buffer memory 6 in parallel, and data SR outputted from MuT2 is compared with expected pattern d from generator 1 by comparator circuit 3. As the result, write signal W to write strobe signal ST and output SR of circuit 3 onto memory 6 by logical operation circuit 5 is generated to write defect information only for disagreement between data SR and pattern d. This operation is repeated up to the end of all patterns, and contents of memory 6 are read out after pattern end, thus analyzing defective address groups.
COPYRIGHT: (C)1980,JPO&Japio
JP13429578A 1978-10-31 1978-10-31 Memory check unit Pending JPS5562598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13429578A JPS5562598A (en) 1978-10-31 1978-10-31 Memory check unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13429578A JPS5562598A (en) 1978-10-31 1978-10-31 Memory check unit

Publications (1)

Publication Number Publication Date
JPS5562598A true JPS5562598A (en) 1980-05-12

Family

ID=15124937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13429578A Pending JPS5562598A (en) 1978-10-31 1978-10-31 Memory check unit

Country Status (1)

Country Link
JP (1) JPS5562598A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130295A (en) * 1981-02-03 1982-08-12 Nec Corp Inspecting device for ic memory
JPS57208697A (en) * 1981-06-16 1982-12-21 Matsushita Electric Ind Co Ltd Semiconductor storage device
JPS61283099A (en) * 1985-06-07 1986-12-13 Hitachi Electronics Eng Co Ltd Memory inspecting data recording system
JPH04177700A (en) * 1990-11-13 1992-06-24 Toshiba Corp Memory fault analysis device
KR100896585B1 (en) * 2000-09-28 2009-05-21 베리지 (싱가포르) 피티이. 엘티디. Memory tester has memory sets configurable for use as error catch ram, tag ram's, buffer memories and stimulus log ram

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5369546A (en) * 1976-12-03 1978-06-21 Fujitsu Ltd Method and apparatus for memory unit test
JPS5558896A (en) * 1978-10-24 1980-05-01 Fujitsu Ltd Analyzer for memory defect

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5369546A (en) * 1976-12-03 1978-06-21 Fujitsu Ltd Method and apparatus for memory unit test
JPS5558896A (en) * 1978-10-24 1980-05-01 Fujitsu Ltd Analyzer for memory defect

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130295A (en) * 1981-02-03 1982-08-12 Nec Corp Inspecting device for ic memory
JPS6220640B2 (en) * 1981-02-03 1987-05-08 Nippon Electric Co
JPS57208697A (en) * 1981-06-16 1982-12-21 Matsushita Electric Ind Co Ltd Semiconductor storage device
JPS61283099A (en) * 1985-06-07 1986-12-13 Hitachi Electronics Eng Co Ltd Memory inspecting data recording system
JPH04177700A (en) * 1990-11-13 1992-06-24 Toshiba Corp Memory fault analysis device
KR100896585B1 (en) * 2000-09-28 2009-05-21 베리지 (싱가포르) 피티이. 엘티디. Memory tester has memory sets configurable for use as error catch ram, tag ram's, buffer memories and stimulus log ram

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