KR940010115A - Memory test device - Google Patents

Memory test device Download PDF

Info

Publication number
KR940010115A
KR940010115A KR1019930020384A KR930020384A KR940010115A KR 940010115 A KR940010115 A KR 940010115A KR 1019930020384 A KR1019930020384 A KR 1019930020384A KR 930020384 A KR930020384 A KR 930020384A KR 940010115 A KR940010115 A KR 940010115A
Authority
KR
South Korea
Prior art keywords
memory
address
failure
defective
detection signal
Prior art date
Application number
KR1019930020384A
Other languages
Korean (ko)
Other versions
KR100212599B1 (en
Inventor
도시미 오자와
Original Assignee
오우라 히로시
가부시키가이샤 아드반테스트
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오우라 히로시, 가부시키가이샤 아드반테스트 filed Critical 오우라 히로시
Publication of KR940010115A publication Critical patent/KR940010115A/en
Application granted granted Critical
Publication of KR100212599B1 publication Critical patent/KR100212599B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56008—Error analysis, representation of errors

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

본 발명은 대용량 메모리의 불량셀의 위치를 단시간에 특정할 수 있는 메모리 시험장치를 제공하는 것을 목적으로 한다.An object of the present invention is to provide a memory test apparatus capable of specifying the location of a defective cell of a large capacity memory in a short time.

피시험 IC와 동등한 메모리 용량을 갖는 불량 해석 메모리(5B)에 대하여 이 불량 해석 메모리(5B)의 정수분의 1의 용량을 가진 압축 격납 메모리(5D)와, 불량 해석 메모리(5B)에 부여하는 어드레스 신호의 임의의 비트를 선택해서 취출하는 어드레스 선택기(5C)를 구비하고, 이 어드레스 선택기(5C)로 선택한 비트의 어드레스 신호에 의하여 압축 격납 메모리(5D)를 액세스하여 불량 위치정보를 기록하는 구조로 구성하고, 압축 격납 메모리(5D)를 독출함으로써 불량셀이 존재하는 블록의 위치를 알고, 이 블록에 대응하는 불량 해석 메모리의 어드레스 영역을 독출함으로써 불량셀의 위치를 특정한다.The defective analysis memory 5B having a memory capacity equivalent to that of the IC under test is provided to the compressed storage memory 5D and the defective analysis memory 5B each having an integral capacity of the defective analysis memory 5B. An address selector 5C which selects and extracts an arbitrary bit of the address signal, and has a structure for accessing the compression storage memory 5D to record defective position information by the address signal of the bit selected by the address selector 5C. By reading the compressed storage memory 5D, the position of the block in which the defective cell exists is known, and the position of the defective cell is specified by reading the address area of the defective analysis memory corresponding to the block.

Description

메모리 시험 장치Memory test device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 일 실시예를 도시하는 블록도,1 is a block diagram showing an embodiment of the present invention;

제2도는 본 발명에 사용한 압축격납 메모리의 내용을 설명하기 위한 도면,2 is a view for explaining the contents of the compression storage memory used in the present invention;

제3도는 본 발명의 변형 실시예를 도시하는 블록도.3 is a block diagram showing a modified embodiment of the present invention.

Claims (2)

피시험 메모리와 같은 어드레스 공간을 가지고, 패턴 발생기로부터 인가되는 어드레스와, 논리 비교기로부터 입력되는 불량 검출 신호에 의하여 불량이 발생한 어드레스에 불량을 표시하는 논리치를 기록할 수 있는 불량 해석 메모리를 구비하여 구성되는 메모리 시험 장치에 있어서, 패턴 발생기로부터 인가되는 어드레스 신호로부터 임의의 비트를 선택가능한 어드레스 선택기와, 그 어드레스 선택기에 의하여 선택된 임의의 비트의 어드레스 신호에 의하여 액세스되고, 논리 비교기로 부터의 불량 검출 신호에 의하여 불량을 표시하는 논리 데이타를 압축해서 격납하는 압축 격납 메모리를 설치한 것을 특징으로하는 메모리 시험 장치.And a failure analysis memory having the same address space as the memory under test and capable of writing a logic value indicating a failure at an address applied by the pattern generator and an address where the failure has occurred due to a failure detection signal input from the logic comparator. A memory test apparatus, comprising: an address selector capable of selecting an arbitrary bit from an address signal applied from a pattern generator, and an address detection signal of an arbitrary bit selected by the address selector, and a failure detection signal from a logic comparator And a compression storage memory for compressing and storing logical data indicating a failure by means of the memory test apparatus. 복수의 피시험 메모리에 동일한 시험패턴신호를 부여하여 각 피시험 메모리에 기록한 데이타를 독출해서 논리 비교기에 부여하고, 논리 비교기로부터 출력되는 불량 검출 신호에 의하여 불량이 발생한 에드레스에 불량을 표시하는 논리치를 기록할 수 있는 불량 해석 메모리를 복수 구비하여 구성되는 메모리 시험 장치에 있어서, 패턴 발생기로부터 인가되는 어드레스 신호로부터 임의의 비트를 선택가능한 어드레스 선택기와, 그 어드레스 선택기에 의하여 선택된 임의의 비트의 어드레스 신호와 논리 비교기로 부터의 불량 검출 신호에 의하여 불량을 나타내는 논리 데이타를 압축하여 격납하는 압축 격납 메모리를 각 불량 해석 메모리 마다에 설치한 것을 특징으로하는 메모리 시험 장치.The same test pattern signal is applied to a plurality of memory under test, the data recorded in each memory to be read is read out, and given to a logic comparator, and the logic for displaying a defect in the address where the defect is generated by the defect detection signal output from the logic comparator A memory test apparatus comprising a plurality of defect analysis memories capable of recording a value, comprising: an address selector capable of selecting an arbitrary bit from an address signal applied from a pattern generator, and an address signal of an arbitrary bit selected by the address selector And a compression storage memory for compressing and storing logical data indicating a failure by a failure detection signal from a logic comparator for each failure analysis memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930020384A 1992-10-05 1993-10-04 Memory test device KR100212599B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4265937A JPH06119799A (en) 1992-10-05 1992-10-05 Device for testing memory
JP92-265937 1992-10-05

Publications (2)

Publication Number Publication Date
KR940010115A true KR940010115A (en) 1994-05-24
KR100212599B1 KR100212599B1 (en) 1999-08-02

Family

ID=17424155

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930020384A KR100212599B1 (en) 1992-10-05 1993-10-04 Memory test device

Country Status (2)

Country Link
JP (1) JPH06119799A (en)
KR (1) KR100212599B1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909448A (en) * 1995-09-22 1999-06-01 Advantest Corporation Memory testing apparatus using a failure cell array
JP3447512B2 (en) * 1997-04-24 2003-09-16 シャープ株式会社 Test method for semiconductor integrated circuit with built-in memory
KR100386626B1 (en) * 2001-02-20 2003-06-02 주식회사 하이닉스반도체 Circuit for testing semiconductor memory
KR100386627B1 (en) * 2001-02-20 2003-06-02 주식회사 하이닉스반도체 Circuit for testing semiconductor memory
KR100772094B1 (en) * 2001-12-28 2007-11-01 주식회사 하이닉스반도체 Semiconductor memory device for test
KR100849776B1 (en) * 2002-07-13 2008-07-31 주식회사 하이닉스반도체 Semiconductor memory device having DQ compress circuit
JP4952160B2 (en) * 2006-09-15 2012-06-13 横河電機株式会社 Semiconductor test equipment
JP4691125B2 (en) * 2008-03-24 2011-06-01 株式会社アドバンテスト Memory test equipment

Also Published As

Publication number Publication date
JPH06119799A (en) 1994-04-28
KR100212599B1 (en) 1999-08-02

Similar Documents

Publication Publication Date Title
KR100542470B1 (en) Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices
KR930005200A (en) Memory module, control method of memory module, and method for setting fault bit table for using memory module
TW353721B (en) Memory tester
KR970075939A (en) Semiconductor memory test method and device
US4866676A (en) Testing arrangement for a DRAM with redundancy
KR960035042A (en) BIST checker and checking method for checking a plurality of memories
KR930014623A (en) Semiconductor memory including redundant memory cell arrays to repair faults
KR930004859A (en) Programmable memory control method and apparatus with error adjustment and test function
EP0324386A3 (en) Memory testing device
KR940006032A (en) Memory card device
KR940022582A (en) Semiconductor Memory with Parallel Bit Test Mode
KR920013472A (en) Semiconductor memory
KR920010653A (en) Memory bad analyzer
EP0600655A3 (en) Integrated circuit test arrangement and method.
US7454662B2 (en) Integrated memory having a circuit for testing the operation of the integrated memory, and method for operating the integrated memory
KR910014951A (en) Memory tester
KR940010115A (en) Memory test device
JP3049343B2 (en) Memory test equipment
KR900013621A (en) Semiconductor device
KR930001067A (en) Small level parity protection method and apparatus for storing data in random access memory
JPS6141028B2 (en)
KR900008517A (en) Dynamic semiconductor memory device and its functional test device and test method
KR910001534B1 (en) Semiconductor memory device
KR930005016A (en) Enabling data access in arbitrary number of bits of semiconductor storage data
CA2340633A1 (en) Memory supervision

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090424

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee