JPS57130295A - Inspecting device for ic memory - Google Patents

Inspecting device for ic memory

Info

Publication number
JPS57130295A
JPS57130295A JP56014877A JP1487781A JPS57130295A JP S57130295 A JPS57130295 A JP S57130295A JP 56014877 A JP56014877 A JP 56014877A JP 1487781 A JP1487781 A JP 1487781A JP S57130295 A JPS57130295 A JP S57130295A
Authority
JP
Japan
Prior art keywords
address
memory
generation part
address information
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56014877A
Other languages
Japanese (ja)
Other versions
JPS6220640B2 (en
Inventor
Atsushi Nigorikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56014877A priority Critical patent/JPS57130295A/en
Publication of JPS57130295A publication Critical patent/JPS57130295A/en
Publication of JPS6220640B2 publication Critical patent/JPS6220640B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To improve the efficiency of a fault analysing means for a mass storage memory by converting addresses of address information from an inspection pattern generation part into one address. CONSTITUTION:Address information outputted from an X address generation part 2 and a Y address generation part 3 in a pattern generator 1 is applied to an IC memory 4 to be measured, whose output signal is compared with expected information generated by the pattern generator 1 by a comparing circuit 5 to made a decision on its propriety. The address information from the address generation parts 2 and 3 is supplied to an X address converting circuit 6 and a Y address converting circuit 7 to obtain one-address information, which is applied to a storage device 8 stored with a judgement result; after all patterns are processed, the contents of the storage device 8 are read to analyze a defective address in the IC memory to be measured.
JP56014877A 1981-02-03 1981-02-03 Inspecting device for ic memory Granted JPS57130295A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56014877A JPS57130295A (en) 1981-02-03 1981-02-03 Inspecting device for ic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56014877A JPS57130295A (en) 1981-02-03 1981-02-03 Inspecting device for ic memory

Publications (2)

Publication Number Publication Date
JPS57130295A true JPS57130295A (en) 1982-08-12
JPS6220640B2 JPS6220640B2 (en) 1987-05-08

Family

ID=11873236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56014877A Granted JPS57130295A (en) 1981-02-03 1981-02-03 Inspecting device for ic memory

Country Status (1)

Country Link
JP (1) JPS57130295A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59207496A (en) * 1983-05-11 1984-11-24 Hitachi Ltd Relief and analysis system for memory defective bit
US5317573A (en) * 1989-08-30 1994-05-31 International Business Machines Corporation Apparatus and method for real time data error capture and compression redundancy analysis

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5558896A (en) * 1978-10-24 1980-05-01 Fujitsu Ltd Analyzer for memory defect
JPS5562598A (en) * 1978-10-31 1980-05-12 Nec Corp Memory check unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5558896A (en) * 1978-10-24 1980-05-01 Fujitsu Ltd Analyzer for memory defect
JPS5562598A (en) * 1978-10-31 1980-05-12 Nec Corp Memory check unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59207496A (en) * 1983-05-11 1984-11-24 Hitachi Ltd Relief and analysis system for memory defective bit
JPH03720B2 (en) * 1983-05-11 1991-01-08 Hitachi Ltd
US5317573A (en) * 1989-08-30 1994-05-31 International Business Machines Corporation Apparatus and method for real time data error capture and compression redundancy analysis

Also Published As

Publication number Publication date
JPS6220640B2 (en) 1987-05-08

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