JPS5561073A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5561073A
JPS5561073A JP13413178A JP13413178A JPS5561073A JP S5561073 A JPS5561073 A JP S5561073A JP 13413178 A JP13413178 A JP 13413178A JP 13413178 A JP13413178 A JP 13413178A JP S5561073 A JPS5561073 A JP S5561073A
Authority
JP
Japan
Prior art keywords
concentration
gaas
film
layer
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13413178A
Other languages
Japanese (ja)
Inventor
Yoshiro Nakayama
Takashi Mimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13413178A priority Critical patent/JPS5561073A/en
Publication of JPS5561073A publication Critical patent/JPS5561073A/en
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To improve high-frequency characteristics and increase gate voltage resistance, by making the carrier concentration of an active layer of FET using GaAs above the degeneration concentration, that is, making the concentration high so that no Schottky barrier is formed.
CONSTITUTION: GaAs high resistance buffer epitaxial layer 2 is grown on semi-insulating substrate 1. On the top of this is grown GaAs active layer 3, 6×1017atoms/ /cm3, whose carrie concentration is made at least above the degeneration concentration. Next, SiO2 film is provided only on the channel region. Using this as mask, the source and drain regions of layer 3 are etched and removed. Subsequently, n+- type GaAs layer, about 3×1018/cm3 in concentration, is grown here, and thereby source and drain electrode contact regions 5, 6 are formed. Then, Au.Ge alloy electrodes 7, 8 are fitted here, film 11 is removed and the entire surface is fitted with SiO2 film. Subsequently, a window is opened, gate oxide film 4 is fitted and gate electrode 9 is provided.
COPYRIGHT: (C)1980,JPO&Japio
JP13413178A 1978-10-31 1978-10-31 Semiconductor device Pending JPS5561073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13413178A JPS5561073A (en) 1978-10-31 1978-10-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13413178A JPS5561073A (en) 1978-10-31 1978-10-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5561073A true JPS5561073A (en) 1980-05-08

Family

ID=15121182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13413178A Pending JPS5561073A (en) 1978-10-31 1978-10-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5561073A (en)

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