JPS54108584A - Manufacture of field effect transistor - Google Patents

Manufacture of field effect transistor

Info

Publication number
JPS54108584A
JPS54108584A JP1554478A JP1554478A JPS54108584A JP S54108584 A JPS54108584 A JP S54108584A JP 1554478 A JP1554478 A JP 1554478A JP 1554478 A JP1554478 A JP 1554478A JP S54108584 A JPS54108584 A JP S54108584A
Authority
JP
Japan
Prior art keywords
film
region
source
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1554478A
Other languages
Japanese (ja)
Inventor
Toshio Sugawa
Takeshi Konuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1554478A priority Critical patent/JPS54108584A/en
Publication of JPS54108584A publication Critical patent/JPS54108584A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To reduce the leakage of gate currents with source DC resistance made small by forming a source-drain region of low resistance while protecting a channel region by an insulator and by insulating the substrate surface between an ohmic electrode provided there and the insulator.
CONSTITUTION: On semi-insulating GaAs substrate 1, N-type GaAs layer 2 is formed by epitaxial growth and onto the gate formation region, Si3N4 film 3 is provided in parallel to the source-drain direction. Next, this is used as a mask to inject N-type impurity ions 4 and after SiO2 protective film 5 is adhered, a heat treatment is carried out to form source region 6' and drain region 6 in layer 2. Then, film 5 is removed by etching leaving film 3 and electrodes 7' and 7 of Au-Ge alloy are adhered onto regions 6' and 6. Next, proton ions are injected into the entire surface to make surface layers 9' and 9 of substrate 1 between electrodes 7' and 7, and film 3 semi-insulated. Then, film 3 is removed and Schottky barrier metal 10 of Al, etc., is adhered onto gate region 3 of layer 2 exposed downward.
COPYRIGHT: (C)1979,JPO&Japio
JP1554478A 1978-02-13 1978-02-13 Manufacture of field effect transistor Pending JPS54108584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1554478A JPS54108584A (en) 1978-02-13 1978-02-13 Manufacture of field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1554478A JPS54108584A (en) 1978-02-13 1978-02-13 Manufacture of field effect transistor

Publications (1)

Publication Number Publication Date
JPS54108584A true JPS54108584A (en) 1979-08-25

Family

ID=11891723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1554478A Pending JPS54108584A (en) 1978-02-13 1978-02-13 Manufacture of field effect transistor

Country Status (1)

Country Link
JP (1) JPS54108584A (en)

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