JPS54108583A - Manufacture of field effect transistor - Google Patents

Manufacture of field effect transistor

Info

Publication number
JPS54108583A
JPS54108583A JP1554378A JP1554378A JPS54108583A JP S54108583 A JPS54108583 A JP S54108583A JP 1554378 A JP1554378 A JP 1554378A JP 1554378 A JP1554378 A JP 1554378A JP S54108583 A JPS54108583 A JP S54108583A
Authority
JP
Japan
Prior art keywords
region
source
gate
metal
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1554378A
Other languages
Japanese (ja)
Other versions
JPS59986B2 (en
Inventor
Toshio Sugawa
Takeshi Konuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1554378A priority Critical patent/JPS59986B2/en
Publication of JPS54108583A publication Critical patent/JPS54108583A/en
Publication of JPS59986B2 publication Critical patent/JPS59986B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To reduce source DC resistance by determining a source-gate region or drain-gate region by self-alignment and by adhering ohmic contact metal onto a gate via Schottky metal when adhering ohmic contact metal onto the source-gate region.
CONSTITUTION: On semi-insulating GaAs substrate 1, N-type GaAs layer 2 is formed by epitaxial growth, and region 3 to be a channel is left by anisotropic etching in parallel to the source-drain region while others are made thin. After N-type impurities are injected into the entire surface via Si3N4 film 4, a heat treatment is carried out to form N+-type gate region 5' in region 3 and N+-type source-drain region 5 in layer 2. Then, the entire surface is covered with resist film 6 except region 5', where Schottky metal 7 of W or the like is adhered, and ohmic contact metal 8 of Au-Ge alloy is adhered to region 5. In this case, metal 8 is formed on metal 7 as well at the same time, and the gate resistance is decreased to improve high-frequency characteristics.
COPYRIGHT: (C)1979,JPO&Japio
JP1554378A 1978-02-13 1978-02-13 Method for manufacturing field effect transistors Expired JPS59986B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1554378A JPS59986B2 (en) 1978-02-13 1978-02-13 Method for manufacturing field effect transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1554378A JPS59986B2 (en) 1978-02-13 1978-02-13 Method for manufacturing field effect transistors

Publications (2)

Publication Number Publication Date
JPS54108583A true JPS54108583A (en) 1979-08-25
JPS59986B2 JPS59986B2 (en) 1984-01-10

Family

ID=11891697

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1554378A Expired JPS59986B2 (en) 1978-02-13 1978-02-13 Method for manufacturing field effect transistors

Country Status (1)

Country Link
JP (1) JPS59986B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59152669A (en) * 1983-02-21 1984-08-31 Mitsubishi Electric Corp Field effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59152669A (en) * 1983-02-21 1984-08-31 Mitsubishi Electric Corp Field effect transistor

Also Published As

Publication number Publication date
JPS59986B2 (en) 1984-01-10

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