JPS5553464A - Method for producing semiconductor element - Google Patents

Method for producing semiconductor element

Info

Publication number
JPS5553464A
JPS5553464A JP12619878A JP12619878A JPS5553464A JP S5553464 A JPS5553464 A JP S5553464A JP 12619878 A JP12619878 A JP 12619878A JP 12619878 A JP12619878 A JP 12619878A JP S5553464 A JPS5553464 A JP S5553464A
Authority
JP
Japan
Prior art keywords
selectively
coated
insulative layer
groove
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12619878A
Other languages
Japanese (ja)
Inventor
Kenji Miyata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12619878A priority Critical patent/JPS5553464A/en
Publication of JPS5553464A publication Critical patent/JPS5553464A/en
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To improve high flequency characteristics of FET by removing an region for forming insulative layer adjacent to a gate region from the side selectively and thereafter forming the insulative layer and closely contacting upper and lower semiconductor region with this insulative layer.
CONSTITUTION: SiO24 is formed on n-type Si substrate by using Si3N4 mask and removed selectively and coated selectively with Si3N45. An opening 3 is etched to form a groove and coated with Si3N48 and opened to the bottom and etched again to form a groove 10. Then surfaces 13, 14 settles as crystalized surfaces (111), (110) and form a groove 11 selectively and fills with SiO2. Then Si3N45 is selectively coated and diffused to form P+-layer 18, n+-layer 20. Finally the film 5 is removed and Al electrodes 21, 22 are formed and n+ drain is diffused from other side of the substrate 1 to accomplish FET. By this construction, gate contact 23 is only exist near channel 24 and other parts are coated with insulative layer and consequently contact capacity Cgs, Cgd become small and flequency charactristics become good.
COPYRIGHT: (C)1980,JPO&Japio
JP12619878A 1978-10-16 1978-10-16 Method for producing semiconductor element Pending JPS5553464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12619878A JPS5553464A (en) 1978-10-16 1978-10-16 Method for producing semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12619878A JPS5553464A (en) 1978-10-16 1978-10-16 Method for producing semiconductor element

Publications (1)

Publication Number Publication Date
JPS5553464A true JPS5553464A (en) 1980-04-18

Family

ID=14929123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12619878A Pending JPS5553464A (en) 1978-10-16 1978-10-16 Method for producing semiconductor element

Country Status (1)

Country Link
JP (1) JPS5553464A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506283A (en) * 1981-05-08 1985-03-19 Rockwell International Corporation Small area high value resistor with greatly reduced parasitic capacitance

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506283A (en) * 1981-05-08 1985-03-19 Rockwell International Corporation Small area high value resistor with greatly reduced parasitic capacitance

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