JPS5538623A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5538623A
JPS5538623A JP10935478A JP10935478A JPS5538623A JP S5538623 A JPS5538623 A JP S5538623A JP 10935478 A JP10935478 A JP 10935478A JP 10935478 A JP10935478 A JP 10935478A JP S5538623 A JPS5538623 A JP S5538623A
Authority
JP
Japan
Prior art keywords
constitution
register
memory
signal
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10935478A
Other languages
Japanese (ja)
Inventor
Takahiko Ogita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10935478A priority Critical patent/JPS5538623A/en
Publication of JPS5538623A publication Critical patent/JPS5538623A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To make it possible to share a memory unit among many systems by providing a register for operation mode information setting inside of the memory unit. CONSTITUTION:Address signals in respective memory array blocks 11A to 11D are given from terminal 101. For operation with constitution of 4K words by X4 bits, memory constitution control circuit 14, when memory constitution information signal 105 is set in memory constitution control holding register 13, makes a connection of write data selector circuit 10 so that write data 102A will be supplied to block 11A through register 3. Further, read data selector circuit 12 is controlled to make read data of block 11A control read data signal 103A through register 6. In case of constitution of 16K words by one bit, only write data signal 102A is made effective by control information set in register 13 by signal 105 and information from 102A is connected to all blocks 11A-11D. Next, circuit 14 allows only one of blocks 11A- 11D to operate and it is connected to 103A.
JP10935478A 1978-09-06 1978-09-06 Memory unit Pending JPS5538623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10935478A JPS5538623A (en) 1978-09-06 1978-09-06 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10935478A JPS5538623A (en) 1978-09-06 1978-09-06 Memory unit

Publications (1)

Publication Number Publication Date
JPS5538623A true JPS5538623A (en) 1980-03-18

Family

ID=14508089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10935478A Pending JPS5538623A (en) 1978-09-06 1978-09-06 Memory unit

Country Status (1)

Country Link
JP (1) JPS5538623A (en)

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