JPS55153321A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55153321A
JPS55153321A JP6170979A JP6170979A JPS55153321A JP S55153321 A JPS55153321 A JP S55153321A JP 6170979 A JP6170979 A JP 6170979A JP 6170979 A JP6170979 A JP 6170979A JP S55153321 A JPS55153321 A JP S55153321A
Authority
JP
Japan
Prior art keywords
wafer
layer
diffused layer
prepared
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6170979A
Other languages
Japanese (ja)
Inventor
Osamu Ishikura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP6170979A priority Critical patent/JPS55153321A/en
Publication of JPS55153321A publication Critical patent/JPS55153321A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To prevent the generation of poor opening and bad heat resistance of a semiconductor device by a method wherein at a back face of a substrate wafer a diffused layer having the same conducting type and a higher concentration is formed, and electrodes are prepared in the diffused layer to obtain a semiconductor having a good ohmic contact property.
CONSTITUTION: An n--type epitaxial wafer doped with an appointed rate of phosphorus is formed on a substrate wafer 1 to form an epitaxial growth layer 11. Insulating films 7, 13 are prepared respectively on both sides of layer, a p-type base region 3 having electrodes is prepared in the growth layer 11, a diffused layer N++ having the same conducting type with the wafer 1 and a higher concentration is formed on the back face the wafer 1, the insulating film 13 is removed and a collector electrode 15 is formed in this diffused layer. By this way, a semiconductor having an extremely good ohmic contact property is obtained, and the generation of poor opening and bad heat resistance can be prevented.
COPYRIGHT: (C)1980,JPO&Japio
JP6170979A 1979-05-18 1979-05-18 Manufacture of semiconductor device Pending JPS55153321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6170979A JPS55153321A (en) 1979-05-18 1979-05-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6170979A JPS55153321A (en) 1979-05-18 1979-05-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55153321A true JPS55153321A (en) 1980-11-29

Family

ID=13179021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6170979A Pending JPS55153321A (en) 1979-05-18 1979-05-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55153321A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS512877A (en) * 1974-06-24 1976-01-10 Dow Corning
JPS5128777A (en) * 1974-09-04 1976-03-11 Hitachi Ltd Kisei pnpn sairisutanohatsuseioboshishita shusekikairosochi no seizohoho

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS512877A (en) * 1974-06-24 1976-01-10 Dow Corning
JPS5128777A (en) * 1974-09-04 1976-03-11 Hitachi Ltd Kisei pnpn sairisutanohatsuseioboshishita shusekikairosochi no seizohoho

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