JPS6425470A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6425470A
JPS6425470A JP18149887A JP18149887A JPS6425470A JP S6425470 A JPS6425470 A JP S6425470A JP 18149887 A JP18149887 A JP 18149887A JP 18149887 A JP18149887 A JP 18149887A JP S6425470 A JPS6425470 A JP S6425470A
Authority
JP
Japan
Prior art keywords
film
opening
etched
mask
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18149887A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18149887A priority Critical patent/JPS6425470A/en
Publication of JPS6425470A publication Critical patent/JPS6425470A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain an excellent bipolar Tr having rare occurrence of crystal defect by filling a fusible insulating film in an opening. CONSTITUTION:A high concentration N<+> type buried layer 2, an N-type epitaxial layer 3 and an oxide film 4 are formed on a P-type semiconductor substrate 1. With a CVD-SiO2 film 5 as a mask a deep opening 6 is formed. The films 5, 4 between the base region and collector contact of a bipolar Tr, and on a field region are etched. Shallow openings 7a, 7b are formed on the layer 3. The films 5, 4 are removed, an oxide film 8 is formed on the whole surface to form a fusible insulating film 9. A resist film 10 is formed on the whole face, the film 10 on the Tr region is etched, and only the resist film on the opening 7b remains. With the film 10 as a mask the film 9 is etched. Accordingly, the film 9 remains only in the opening.
JP18149887A 1987-07-21 1987-07-21 Manufacture of semiconductor device Pending JPS6425470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18149887A JPS6425470A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18149887A JPS6425470A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6425470A true JPS6425470A (en) 1989-01-27

Family

ID=16101811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18149887A Pending JPS6425470A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6425470A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4988639A (en) * 1988-09-28 1991-01-29 Nec Corporation Method of manufacturing semiconductor devices using trench isolation method that forms highly flat buried insulation film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4988639A (en) * 1988-09-28 1991-01-29 Nec Corporation Method of manufacturing semiconductor devices using trench isolation method that forms highly flat buried insulation film

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