JPS55146943A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS55146943A JPS55146943A JP5437679A JP5437679A JPS55146943A JP S55146943 A JPS55146943 A JP S55146943A JP 5437679 A JP5437679 A JP 5437679A JP 5437679 A JP5437679 A JP 5437679A JP S55146943 A JPS55146943 A JP S55146943A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- introducing
- separation layer
- used alone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 abstract 7
- 229910052742 iron Inorganic materials 0.000 abstract 3
- 229910052750 molybdenum Inorganic materials 0.000 abstract 3
- 238000000926 separation method Methods 0.000 abstract 3
- 239000006185 dispersion Substances 0.000 abstract 2
- 229910052737 gold Inorganic materials 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 229910052759 nickel Inorganic materials 0.000 abstract 2
- 229910052697 platinum Inorganic materials 0.000 abstract 2
- 229910052725 zinc Inorganic materials 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000004904 shortening Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To reduce leak voltage and eliminate element to element separation layer, by introducing one of Au, Fe or Mo and also one of Zn, Co, Ni or Pt, and by using thus processed intrinsic semiconductor substrate. CONSTITUTION:In order to prevent deterioration of integration effect due to shortening of dispersion time and formation of the separation layer extending from an epitaxial layer surface to a substrate on an Si substrate, while intrinsic process is conducted by dispersing 1 of Au, Fe or Mo on the substrate and the epitaxial layer keeping donor sequence on the center of prohibited zone, as dispersion control is difficult and Au can easily accumulate on the substrate surface if it is used alone, Mo and Fe can hardly be neutralized uniformly if they are used alone because of their thin surfaces. By introducing 1 of Zn, Co, Ni or Pt, efficiency for these ions to be arranged in positions between gratings can be improved and intrinsic process can be achieved uniformly on an entire surface of the substrate, and therefore, leak voltage of the substrate can be reduced and the separation layer becomes unnecessary. Further, by providing p<+>-layer or n<+>-layer, n<->-layer or p<->-layer is formed on the boundary enabling C-MOS to be formed without p well.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5437679A JPS55146943A (en) | 1979-05-02 | 1979-05-02 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5437679A JPS55146943A (en) | 1979-05-02 | 1979-05-02 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55146943A true JPS55146943A (en) | 1980-11-15 |
Family
ID=12968948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5437679A Pending JPS55146943A (en) | 1979-05-02 | 1979-05-02 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55146943A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57162359A (en) * | 1981-03-30 | 1982-10-06 | Toshiba Corp | Semiconductor device |
-
1979
- 1979-05-02 JP JP5437679A patent/JPS55146943A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57162359A (en) * | 1981-03-30 | 1982-10-06 | Toshiba Corp | Semiconductor device |
| JPS6359545B2 (en) * | 1981-03-30 | 1988-11-21 |
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