JPS55140248A - Method of packaging semiconductor device - Google Patents

Method of packaging semiconductor device

Info

Publication number
JPS55140248A
JPS55140248A JP4796279A JP4796279A JPS55140248A JP S55140248 A JPS55140248 A JP S55140248A JP 4796279 A JP4796279 A JP 4796279A JP 4796279 A JP4796279 A JP 4796279A JP S55140248 A JPS55140248 A JP S55140248A
Authority
JP
Japan
Prior art keywords
frame
semiconductor device
package
base
package base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4796279A
Other languages
Japanese (ja)
Inventor
Shunichiro Fujioka
Shunei Uematsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4796279A priority Critical patent/JPS55140248A/en
Publication of JPS55140248A publication Critical patent/JPS55140248A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PURPOSE:To prevent occurrence of improper package of a semiconductor device by bonding the flat portion between a package base and a frame with glass, bending the lead wire by utilizing the adhering strength and an auxiliary pressing force by a jig and attaching a cover thereon. CONSTITUTION:A flat frame 3 is mounted on a package base 2 secured with a semiconductor pellet 1 thereto and connected to a wire 4. A lead wire 5 is secured via a jig 6 by utilizing the adhering strength of the frame 3 to the base 2 and bent in predetermined shape. According to this method, the package base 2 can be effectively isolated from the frame 3. A cover 3 is finally coated thereon.
JP4796279A 1979-04-20 1979-04-20 Method of packaging semiconductor device Pending JPS55140248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4796279A JPS55140248A (en) 1979-04-20 1979-04-20 Method of packaging semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4796279A JPS55140248A (en) 1979-04-20 1979-04-20 Method of packaging semiconductor device

Publications (1)

Publication Number Publication Date
JPS55140248A true JPS55140248A (en) 1980-11-01

Family

ID=12789959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4796279A Pending JPS55140248A (en) 1979-04-20 1979-04-20 Method of packaging semiconductor device

Country Status (1)

Country Link
JP (1) JPS55140248A (en)

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