JPS55105357A - Mis semiconductor device and its manufacture - Google Patents

Mis semiconductor device and its manufacture

Info

Publication number
JPS55105357A
JPS55105357A JP1241079A JP1241079A JPS55105357A JP S55105357 A JPS55105357 A JP S55105357A JP 1241079 A JP1241079 A JP 1241079A JP 1241079 A JP1241079 A JP 1241079A JP S55105357 A JPS55105357 A JP S55105357A
Authority
JP
Japan
Prior art keywords
layer
layers
silicon
insulating
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1241079A
Other languages
Japanese (ja)
Inventor
Michiyuki Harada
Kunio Owada
Mamoru Kondo
Toru Araki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1241079A priority Critical patent/JPS55105357A/en
Publication of JPS55105357A publication Critical patent/JPS55105357A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

PURPOSE:To obtain a MIS device with a large scale integration by a simple process by providing amorphous or polycrystal silicon layer to the selected opening of insulating film on the silicon substrate and by forming SiO2 film on the surface of said layer by oxidizing it. CONSTITUTION:The insulating thin layers 4 surrounded by the insulating film 3 are arranged in the form of a matrix on the n-type silicon substrate 2, Mo masks 5, 6 are formed to selectively give the resist mask 7 to the layer 4. After the insulating layer 4 is opened, the mask 7 is removed, and the opening is covered with amorphous or polycrystal silicon. Next ions are implated into the said silicon layer to make it p-type ones 13, 14, and Mo masks 5, 6 are removed. The surface of the layers 13, 14 are oxidized, silicon layers 19, 21, insulating layers 20, 22, and p-type layer 23 are formed, the metal layer 24 is provided in the lateral direction on the layers 3, 30, 22 last. In this way, a MIS device with a large scale integration, in which the storage elements that consist of the MISFETs and capacity elements are arranged in the form of a matrix, can be obtained by a simple process.
JP1241079A 1979-02-06 1979-02-06 Mis semiconductor device and its manufacture Pending JPS55105357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1241079A JPS55105357A (en) 1979-02-06 1979-02-06 Mis semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1241079A JPS55105357A (en) 1979-02-06 1979-02-06 Mis semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS55105357A true JPS55105357A (en) 1980-08-12

Family

ID=11804482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1241079A Pending JPS55105357A (en) 1979-02-06 1979-02-06 Mis semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS55105357A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59113659A (en) * 1982-12-20 1984-06-30 Toshiba Corp Mos dynamic memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59113659A (en) * 1982-12-20 1984-06-30 Toshiba Corp Mos dynamic memory

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