JPS59113659A - Mos dynamic memory - Google Patents

Abstract

PURPOSE:To eliminate contact holes, to dissolve the problem of contact resistance, to simplify the manufacturing process and to obtain an MOS dynamic memory of high performance at low cost by a method wherein the combination gate electrode and word line of a switching transistor is formed. CONSTITUTION:After an Si3N4 film pattern, an oxide film pattern, N<+> type impurity regions 6, 7, etc., are formed in order on the surface of a P type silicon substrate 1, a thermally oxide film 12 is formed thick on the surface of a polycrystalline silicon pattern 11 and thin on the surface of the substrate 1. At this time, phosphorus is thermally diffused from the silicon pattern 11 to form an N<+> type impurity region 13 under the drain region 7. Then after an Al film is evaporated on the whole surface, patterning is performed to form the gate electrode 14 of a switching transistor to be used both as a word line. Then a protective film is coated on the whole surface to manufacture an MOS dynamic memory. At the MOS dynamic memory thereof, the channel length direction of the switching transistor and the wiring direction of the word line are formed making the angle of 45 degrees. When the angle thereof is in the extent of 30- 60 degrees, a high degree of integration can be held.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to improvements in MOS dynamic memory.

[Technical background of the invention and its problems]

MOS dynamic memory was developed by IK in 1970)
Since dRAM was put into practical use, the capacity has increased fourfold in 73 years, and mass production of dRAM is currently underway at a rate of 64. In addition, d of 256 bits and 1M bits will be added in the future.
There is no doubt that it will evolve into RAM.

In this way, there are still some important problems that need to be solved when high-density A'ri is achieved, that is, the ability to miniaturize elements. Common solutions are listed below.

(1) If the effective channel length varies from memory cell to memory cell, the sensitivity of the sense amplifier will be significantly reduced. Therefore, it is important to make the effective channel length as independent as possible from alignment errors between masks.

(ii) It is desirable to increase the utilization efficiency of the memory capacitor per unit cell, that is, the ratio of the occupied area. Regarding this problem, if the bit line is formed with an impurity diffusion layer running on the substrate surface, the ratio of the area occupied by the capacitor will be reduced, so the bit line (polycrystalline silicon or gold M'
It is desirable to form using e. Furthermore, by reducing the number of impurity diffusion layers, soft errors can be reduced.

(iii) Word line signal delays occur because word lines inevitably become longer as capacity increases.

In order to prevent this word line signal delay, it is considered optimal to use a low resistance metal for the word line.

40 With higher integration, contact holes become smaller and the contact resistance can no longer be ignored, making it impossible to expect normal operation.

To reduce contact resistance to prevent this,
Although this goes against the grain of high integration, it is necessary to make only the contact hole larger, or to make the contact hole smaller but with a smaller resistance.

(v) Considering cost reduction and yield improvement, it is important to reduce the number of steps.

To address the above problems, the current most common two-layer polycrystalline silicon gate structure is that the capacitor electrode is formed using the first layer of polycrystalline silicon, and the dirt electrode of the switching transistor is formed using the second layer of polycrystalline silicon. If we consider the dRAM, we get the following.

Regarding (i), currently, manufacturing methods are mainly used in which the effective channel length depends on the alignment accuracy of the first layer of polycrystalline silicon and the second layer of polycrystalline silicon.
By improving the manufacturing method, the effective channel length can be made constant.

Regarding (ii), the current mainstream is a structure in which the bit line is formed by an impurity diffusion layer, which not only has a low utilization efficiency of the memory capacitor per cell area but also is susceptible to soft errors. However, several proposals have been made, including those using At or polycrystalline silicon for the bit line.

(Iill uses At for the word line in order to prevent signal delay on the word line for those that guarantee high-speed read or write time.

9 is not so much of a problem with 1 at present, but it is thought that it will become the most important problem as miniaturization progresses in the future.

Regarding 0, in the current process, the dirt electrode of the switching transistor is formed from the second layer of polycrystalline silicon,
Since the FI'Q is connected to At used as a word line through a contact hole, a large number of steps are required and complicated processing must be performed.

As mentioned above, as integration progresses in the future, it is thought that the above problems (φ and (V)) will become most important.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a high-performance, low-cost MOS dynamic memory that solves the problem of contact resistance, can be manufactured in a simplified process, and is capable of providing high performance and low cost.

[Summary of the invention]

The MOS dynamic memory of the present invention includes first and second second conductivity type (N+ type) impurity regions formed on the surface of a first conductivity type, for example, P type, semiconductor substrate, and the first N+ type impurity region ( a bit line formed in direct contact with the surface of the second N-type impurity region (the source or drain region of the switching transistor); polycrystalline silicon i+ turn, and the first and second
The device is characterized in that it includes a dirt electrode of a switching transistor which also serves as a word line, formed on the semiconductor substrate between the resistant impurity regions via a Y-t insulating film.

Since the dirt electrode of the switching transistor is also used as a word line in this way, there is no need to open a contact hole to connect the two as in the conventional case, and the problem of contact resistance does not occur. Moreover, the manufacturing process can also be simplified.

[Embodiments of the invention]

Examples of the present invention will be described below in Figures 1 (,) to (g) and 2.
This will be explained with reference to Figures (a) to (,). In addition, Figure 1 (
a) j (b) t (e) e (e) and (g)
are sectional views taken along the line 1-1#il in FIGS. 2(a) to 2(,), respectively, and show one memory cell and part of another memory cell adjacent thereto.

First, a thermal oxide film and Si
, N4 films were sequentially formed, and then a photoresist pattern (not shown) was formed on the device area. Next, using this photoresist non-turn as a mask, the Si, N4 film and thermal oxide film were sequentially etched to form a Si, N4 film pattern 2 and an oxide film pattern 3. Subsequently, after removing the photoresist pattern, thermal oxidation is performed using the 513N4 film turn 2 as an oxidation-resistant mask,
A field oxide film 4 was formed (as shown in FIG. 10 and FIG. 2(a)).

Next, the Si 3N4 film pattern 2 and the oxide film
After sequentially removing the mother turns 3 by etching, a thermal oxide film 5 having a thickness of 200× was formed on the surface of the element region. Subsequently, a photoresist/mother turn (not shown) was formed on the intended channel region of the switching transistor, and then an N-type impurity such as arsenic was ion-implanted using the photoresist pattern as a mask. Subsequently, after removing the photoresist pattern, heat treatment is performed to form a first impurity type impurity region 6 that also serves as the substrate side electrode of the capacitor and a second type impurity region 6 that is shared by two memory cells and serves as the source or drain of the switching transistor. An impurity region 7 was formed (as shown in FIGS. 1(b) and 2).

Next, after depositing a first layer of polycrystalline silicon film over the entire surface, phosphorus was thermally diffused to lower the resistance. Next, this polycrystalline silicon film is turned to form a capacitor electrode 8, and the thermal oxide film 5 is etched using this capacitor electrode as a mask to form an oxide film i4 turn 9.
was formed (as shown in FIG. 1(C) and FIG. 2(, )).

Next, thermal oxidation was performed to form a thick thermal oxide film 10 on the surface of the capacitor electrode 8 and a thin thermal oxide film 10 on the surface of the substrate 1, taking advantage of the difference in oxidation rate between polycrystalline silicon and the silicon substrate (see FIG. 1(d)). ).

Next, after etching only a thin portion of the thermal oxide film 10 on the surface of the substrate 1, a second layer of polycrystalline silicon film was deposited on the entire surface, and phosphorous was ion-implanted to lower the resistance. Subsequently, this polycrystalline silicon film was patterned to form a polycrystalline silicon pattern 11 that would become a bit line in direct contact with the second ON+ type impurity region 7 (see FIG. 1(a) and FIG. 2(d)). ).

Next, thermal oxidation is performed, taking advantage of the difference in oxidation rate between the polycrystalline silicon and the silicon substrate to thermally oxidize the polycrystalline silicon to be thicker on the surface of the mother turn 11 and thinner on the surface of the substrate 1.
<q J,? was formed. At this time, phosphorus was thermally diffused from the polycrystalline silicon pattern 11 to form an N+ type impurity region 13 under the drain region 7 (Fig. 1(f)
).

Next, after depositing a kA film on the entire surface, it is patterned to form a switching transistor (ff-) that also serves as a word line.
'R pole 14 was formed. Here, the channel length direction of the switching transistor and the wiring direction of the word line are 45°.
(as shown in Figures 1(g) and 2(a)).

Next, a MOS dynamic memory was manufactured by covering the entire surface with a protective layer.

The MOS dynamic memory shown in FIGS. 1(g) and 2(a) has a dirt electrode 14 of a switching transistor.
is also used as a word line. On the other hand, in order to increase the degree of integration in this manner, if the pattern shape of the memory cell is the same as that of a conventional MOS dynamic memory, wiring of word lines becomes difficult. For this reason, the MOS dynamic memory is formed so that the channel length direction of the switching transistor and the wiring direction of the word line form an angle of 45 degrees. The angle between the channel length direction of this switching transistor and the wiring direction of the word line is 30~
A high degree of integration can be maintained within the range of 60 degrees.

Therefore, the above-mentioned MOS dynamic memory has the following effects.

(1) Dirt electrode 14 of switching transistor
is also used as a word line, so conventional MOS
Unlike a dynamic memory, there is no need to form a contact hole for connecting the r-) electrode and the word line, and the operating characteristics are not adversely affected by contact resistance.

Further, since the dirt electrode 14 and the word line are formed at the same time and there is no need to form a contact hole, the number of photolithographic steps can be reduced by two.

Therefore, it greatly contributes to cost reduction and reliability improvement. Furthermore, since At is used as one word line, signal delay is small.

(11) Since the bit line is formed by slightly turning the second layer of polycrystalline silicon, the ratio of the area occupied by the capacitor and the capacitor is lower than that when the bit line is formed by an impurity diffusion layer. can be increased by 20 to 30 inches.

(iii) The incidence of soft errors due to alpha rays is reduced by the amount that the area of the impurity diffusion layer is reduced.

49 Since the polycrystalline silicon pattern 11 serving as the bit line is in direct contact with the second ON+ type impurity region 7, there is no need to form a contact hole as in the conventional MOS dynamic memory.

Therefore, the contact area between the bit line and the second N+ type impurity region does not decrease and the contact resistance does not increase.

0 According to the above method for manufacturing a MOS dynamic memory, the switching transistor is The effective channel length is uniquely determined and is not affected by mask alignment errors between the capacitor electrode 8 and the f-) electrode 14. Therefore, there is no variation in the effective channel length of the switching transistor of each memory cell, and the sense sensitivity of each memory cell is constant, which greatly contributes to improving the yield of products.

In the above embodiment, a thermal oxide film was used as an insulating film formed on the surface of the key Al lower electrode 8 and the polycrystalline silicon pattern 110 which becomes the bit line, but polycrystalline silicon and C
It may also be a step of sequentially depositing VD-8iO2 films, then sequentially turning them, and then performing thermal oxidation to oxidize the edges of the polycrystalline silicon.

Further, in the above embodiment, metal (At) is used as the dirt electrode of the switching transistor that also serves as a word line, but the material is not limited to this, and polycrystalline silicon or metal silicide may be used.

〔Effect of the invention〕

As described in detail above, according to the present invention, by forming the dart electrode of the switching transistor and the word line, it is possible to eliminate the υ contact hole, solve the problem of contact resistance, and simplify the manufacturing process. , it is possible to provide a high-performance, low-cost MOS dynamic memory.

[Brief explanation of the drawing]

Figures 1(,) to (g) show MOS in the embodiment of the present invention.
A cross-sectional view showing the manufacturing process of dynamic memory, Figure 2 (
, ) to (,) are the same plan views. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 4... Field oxide film, 6... First sapon type impurity region, 7... Second t-type impurity region, 8... Capacitor electrode, 9... ...Oxide film or turn, 10,12...Thermal oxide film, 11...Polycrystalline silicon or turn (bit line), 13...N+
Type impurity region, 14... dirt electrode (word line). Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 1

Claims (2)

[Claims] (1) first and second second conductivity type impurity regions formed on the surface of a first conductivity type semiconductor substrate; a capacitor electrode formed on the first impurity region with an insulating film interposed therebetween; A polycrystalline silicon nof turn serving as a bit line is formed in direct contact with the surface of the second impurity region, and a dirt insulating film is formed on the semiconductor substrate between the first and second impurity regions. A MOS characterized by comprising a dirt electrode of a switching transistor that also serves as a word line.
dynamic memory. (2) The second second conductivity type impurity region is shared by two switching transistors, and the wiring direction of the dirt electrode that also serves as a word line forms an angle of 30 to 60 degrees with respect to the channel length direction of the switching transistor. M according to claim 1, characterized in that it is provided as follows.
OS dynamic memory.