JPH01175765A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH01175765A JPH01175765A JP62335695A JP33569587A JPH01175765A JP H01175765 A JPH01175765 A JP H01175765A JP 62335695 A JP62335695 A JP 62335695A JP 33569587 A JP33569587 A JP 33569587A JP H01175765 A JPH01175765 A JP H01175765A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- layer
- band metal
- band
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000012528 membrane Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 63
- 239000011229 interlayer Substances 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 238000002844 melting Methods 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- 229910021332 silicide Inorganic materials 0.000 abstract description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910021341 titanium silicide Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明はデジタル情報を記憶させるマスクＲＯＭに関す
るものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a mask ROM for storing digital information.
（従来技術）
現存するマスクＲＯＭの殆んどはｌＭＯＳトランジスタ
を主構成要素としているので、チャネル領域の確保やチ
ャネルとコンタクトの間の距離の確保などが製造技術上
必要であり、メモリセル面積を縮小することが困難であ
り、また、読出し速度も遅い欠点がある。(Prior art) Since most of the existing mask ROMs have IMOS transistors as their main components, it is necessary to secure a channel region and a distance between the channel and the contact in terms of manufacturing technology, which reduces the memory cell area. It is difficult to reduce the size and has the disadvantage that the read speed is slow.
そこで、複数本の帯状多結晶シリコン層と複数本の帯状
導電層とのそ丘ぞれを絶縁膜を介して交差させ、その交
点に記憶情報に応じて適宜コンタクトを設けるとともに
、そのコンタクトにＰＮ接合を形成したマスクＲＯＭが
提案されている（特公昭６１−１９０４号公報参照）。Therefore, the ridges of a plurality of strip-shaped polycrystalline silicon layers and a plurality of strip-shaped conductive layers are made to intersect with each other via an insulating film, contacts are provided at the intersection points as appropriate depending on the stored information, and the contacts are connected to PN. A mask ROM in which a junction is formed has been proposed (see Japanese Patent Publication No. 61-1904).
しかしながら、上記引例のマスクＲＯＭでは、ワードラ
インとビットラインの一方は多結晶シリコン層であるた
め、比較的抵抗値が高く、メモリ装置を大容量化した場
合に高速性を実現することは困難である。However, in the mask ROM cited above, one of the word line and bit line is a polycrystalline silicon layer, which has a relatively high resistance value, making it difficult to achieve high speed when increasing the capacity of the memory device. be.
（目的）
本発明はワードラインとビットラインの交点にＰＮ接合
を形成し、コンタクトの有無によってプログラムを施す
ことによってメモリ容量を大きくしたマスクＲＯＭにお
いて、高速性を実現することを目的とするものである。(Purpose) The present invention aims to achieve high speed in a mask ROM with increased memory capacity by forming a PN junction at the intersection of a word line and a bit line and performing programming depending on the presence or absence of contact. be.
（構成）
本発明では、基板表面上に互いに平行に設けられた複数
本の第１の帯状金属層の上部に絶縁膜を介して互いに平
行に、かつ、第１の帯状金属層と直交する方向に複数本
の第２の帯状金属層が設けられ、第１の帯状金属層と第
２の帯状金属層の交点には第１の帯状金属層と前記絶縁
膜との間にＰ型半導体層とＮ型半導体層が積層して形成
されてＰＮ接合が形成されており、第１の帯状金属層と
第２の帯状金属層の交点の前記絶縁膜には記憶すべき情
報に応じてコンタクト孔が形成されている。(Structure) In the present invention, a plurality of first strip-shaped metal layers provided parallel to each other on the surface of the substrate are provided on top of the plurality of first strip-shaped metal layers with an insulating film interposed therebetween, in a direction parallel to each other and orthogonal to the first strip-shaped metal layers. A plurality of second band-shaped metal layers are provided at the intersection of the first band-shaped metal layer and the second band-shaped metal layer, and a P-type semiconductor layer is provided between the first band-shaped metal layer and the insulating film. A PN junction is formed by stacking N-type semiconductor layers, and a contact hole is formed in the insulating film at the intersection of the first strip-shaped metal layer and the second strip-shaped metal layer according to the information to be stored. It is formed.
以下、実施例について具体的に説明する。Examples will be specifically described below.
第１図は一実施例の部分平面図、第２図は第１図のＸ−
Ｘ線位置での断面図である。FIG. 1 is a partial plan view of one embodiment, and FIG. 2 is a
FIG. 3 is a cross-sectional view at an X-ray position.
基板ｌ上に、互いに平行で第１図で横方向に延びる帯状
金属層２−１．２−２．・・・・・・が形成されている
。金属層２−１．２−２．・・・・・・とじては高融点
金属又はそのシリサイドで、抵抗値の低いものが適当で
ある。金属層２の上部には眉間絶縁膜３を介して、互い
に平行で、第１図で縦方向に延びる帯状金属層４−１．
４−２．・・・・・・が形成されている。したがって、
金属層２−１．２−２．・・・・・・の延びる方向に対
して金属層４−１．４−２゜・・・・・・の延びる方向
は直交している。金属層４−１゜４−２．・・・・・・
とじてはアルミニウムの他、Ａｆｌ−８ｉのようなアル
ミニウム合金などを使用することができる。眉間絶縁膜
３としては例えばＰＳＧ膜を使用することができる。On the substrate l, strip-shaped metal layers 2-1, 2-2. parallel to each other and extending laterally in FIG. ... is formed. Metal layer 2-1.2-2. ...A high melting point metal or its silicide with a low resistance value is suitable for the material. On the upper part of the metal layer 2, a band-shaped metal layer 4-1.
4-2. ... is formed. therefore,
Metal layer 2-1.2-2. The extending direction of the metal layers 4-1.4-2° is perpendicular to the extending direction of the metal layers 4-1.4-2°. Metal layer 4-1°4-2.・・・・・・
In addition to aluminum, an aluminum alloy such as Afl-8i can be used for the closure. For example, a PSG film can be used as the glabellar insulating film 3.
金属層２−１．２−２．・・・・・・と金属層４−１゜
４−２．・・・・・・の交点には、金属層２−１．２−
２゜・・・・・・上にＰＮ接合を形成するために、Ｐ型
ポリシリコン層５とＮ型ポリシリコン層６が積層して形
成されている。そして、ＰＮ接合の上部の層間絶縁膜３
には、記憶すべき情報に応じコンタクト孔７が形成され
、コンタクト孔７が形成された交点では金属層４−１．
４−２．・・・・・・とＮ型ポリシリコン層６とが接触
している。Metal layer 2-1.2-2. ...and metal layer 4-1゜4-2. At the intersection of . . . , there is a metal layer 2-1.2-
2°... In order to form a PN junction thereon, a P-type polysilicon layer 5 and an N-type polysilicon layer 6 are laminated. Then, the interlayer insulating film 3 above the PN junction
, a contact hole 7 is formed in accordance with the information to be stored, and at the intersection where the contact hole 7 is formed, the metal layer 4-1 .
4-2. ... is in contact with the N-type polysilicon layer 6.
金Ｊ）１Ｍ２−１．２−２．・・・・・・と金属Ｍ４−
１゜４−２．・・・・・・の一方をビットラインとし、
他方をワードラインとする。Gold J) 1M2-1.2-2. ...and metal M4-
1°4-2. One side of ... is the bit line,
The other side is the word line.
第３図に本実施例のメモリセルを含むメモリ装置を示す
、第３図で鎖線で示された領域Ｃは第１図に示された６
個のメモリセルに対応している。FIG. 3 shows a memory device including the memory cell of this embodiment. Area C indicated by a chain line in FIG.
It corresponds to 1 memory cell.
この例では金属層２−１．２−２．・・・・−がビット
ラインＢＬＯ，ＢＬＩ、・・・・・・に対応し、金属層
４−１．４−２．・・・・・・がワードラインＷＬＯ，
ＷＬｌ、・・・・・・に対応している。In this example, metal layers 2-1.2-2. . . . corresponds to bit lines BLO, BLI, . . . and metal layers 4-1, 4-2. ...is the word line WLO,
Compatible with WLl,...
８はワードラインＷＬＯ，ＷＬＩ、・・・・・・を選択
するＸデコーダであり１選択したワードラインをＬレベ
ルにし、他をＨレベルにする。９はＹデコーダであり、
Ｙゲート１０を介してビットラインＢＬＯ２ＢＬ１．・
・・・・・を選択し１選択したビットラインをセンスア
ンプ１１に接続する。センスアンプ１１はビットライン
ＢＬＯ，ＢＬＩ、・・・・・・の電圧又は電流を感知し
増幅する。8 is an X decoder for selecting word lines WLO, WLI, . . . , which sets one selected word line to L level and sets the others to H level. 9 is a Y decoder;
Bit lines BLO2BL1 .・
. . . and connect the selected bit line to the sense amplifier 11. The sense amplifier 11 senses and amplifies the voltage or current of the bit lines BLO, BLI, . . . .
メモリセル部においては１例えばメモリセルＡでは眉間
絶縁膜３にコンタクト孔７が存在しないので、Ｘデコー
ダ８によりワードラインＷＬＯが選択され、Ｙデコーダ
９によりビットラインＢＬＯが選択されても、ビットラ
インＢＬＯからワードラインＷＬＯに電流は流れず、し
たがって、ビットラインＢＬＯの電位はＨレベルを維持
する。In the memory cell section, for example, in memory cell A, there is no contact hole 7 in the glabellar insulating film 3, so even if the word line WLO is selected by the X decoder 8 and the bit line BLO is selected by the Y decoder 9, the bit line No current flows from BLO to word line WLO, so the potential of bit line BLO remains at H level.
一方１例えばメモリセルＢでは眉間絶縁膜３にコンタク
ト孔７が設けられているので、Ｘデコーダ８によりワー
ドラインＷＬＩが選択され、Ｙデコーダ９によりビット
ラインＢＬＯが選択されると、ビットラインＢＬＯから
ワードラインＷＬＩに電流が流れてビットラインＢＬＯ
の電位がＬレベルになる。On the other hand, in memory cell 1, for example, contact hole 7 is provided in glabellar insulating film 3, so when word line WLI is selected by X decoder 8 and bit line BLO is selected by Y decoder 9, from bit line BLO to Current flows through the word line WLI and the bit line BLO
The potential of becomes L level.
このように、Ｘレコーダ８でいずれかのワードラインＷ
ＬＯ，ＷＬＩ、・・・・・・を選択し、Ｙレコーダ９で
いずれかのビットラインＢＬＯ，ＢＬＩ。In this way, the X recorder 8 selects one of the word lines W.
LO, WLI, . . . are selected, and the Y recorder 9 selects one of the bit lines BLO, BLI.
・・・・・・を選択すれば、その交点のメモリセルの記
憶情報を読み出すことができる。By selecting . . . , the stored information of the memory cell at the intersection can be read out.
次に、第４図により一実施例のメモリセルを製造する方
法を説明する。Next, a method for manufacturing the memory cell of one embodiment will be explained with reference to FIG.
（Ａ）半導体集積回路装置を製造する従来のプロセスに
よって、単結晶シリコン基板２０の表面にフィールド酸
化膜２１を形成する。この例ではメモリセル部において
は、ビットライン（又はワードライン）である下層の金
属層ごとにフィールド酸化膜２１で分離する。(A) A field oxide film 21 is formed on the surface of a single crystal silicon substrate 20 by a conventional process for manufacturing a semiconductor integrated circuit device. In this example, in the memory cell portion, each underlying metal layer, which is a bit line (or word line), is separated by a field oxide film 21.
（Ｂ）メモリセル部ではチャネルドープを施し、周辺ト
ランジスタ部ではゲート酸化膜を形成した後、メモリセ
ル部でタングステンを選択的に堆積したり、又はチタン
シリサイドを選択的に形成することにより、ビットライ
ン（又はワードライン）２２を形成する。タングステン
は基板２０のシリコンが露出した部分のみに堆積し、フ
ィールド酸化膜２１上には堆積しない、チタンシリサイ
ドの場合は、全面にチタンを堆積し、基板２０のシリコ
ンが露出した部分で反応させてチタンシリサイドを形成
させ、フィールド酸化膜２１上のチタンのみを溶媒に溶
解させて除去する。(B) After channel doping is performed in the memory cell area and a gate oxide film is formed in the peripheral transistor area, bits are formed by selectively depositing tungsten or selectively forming titanium silicide in the memory cell area. A line (or word line) 22 is formed. Tungsten is deposited only on the exposed silicon portion of the substrate 20 and not on the field oxide film 21. In the case of titanium silicide, titanium is deposited on the entire surface and reacted on the exposed silicon portion of the substrate 20. Titanium silicide is formed, and only the titanium on the field oxide film 21 is dissolved in a solvent and removed.
（Ｃ）その後、Ｐ型ポリシリコン層２３とＮ型ポリシリ
コン層２４を順次ＬＰＣＶＤ法により堆積し、写真製版
とエツチングによってパターン化する。なお、（Ｃ）以
降のメモリセル部はＣＢ）の鎖線で囲まれた部分に対応
する部分を拡大して示しである。(C) Thereafter, a P-type polysilicon layer 23 and an N-type polysilicon layer 24 are sequentially deposited by the LPCVD method, and patterned by photolithography and etching. Note that the memory cell portions shown in (C) and later are enlarged views of the portions corresponding to the portions surrounded by the chain lines in (CB).
このとき１周辺トランジスタ部ではＮ型ポリシリコン層
２４を形成するときに同時にポリシリコンゲート２４ａ
を形成する。At this time, in the first peripheral transistor section, when forming the N-type polysilicon layer 24, the polysilicon gate 24a is simultaneously formed.
form.
（Ｄ）周辺トランジスタ部でイオン注入法や拡散法によ
って基板２０にＮ型不純物を導入して拡散領域２５．２
６を形成する。(D) In the peripheral transistor section, N-type impurities are introduced into the substrate 20 by ion implantation or diffusion to form a diffusion region 25.2.
form 6.
その後、層間絶縁膜としてＰＳＧ膜２７を堆積する。Thereafter, a PSG film 27 is deposited as an interlayer insulating film.
写真製版とエツチングにより、メモリセル部では記憶す
べき情報に応じてＰＳＧ膜２７のＰＮ接合上にコンタク
ト孔２８を形成し、周辺トランジスタ部ではソース電極
及びドレイン電極を形成するためのコンタクト孔２９を
形成する。By photolithography and etching, a contact hole 28 is formed on the PN junction of the PSG film 27 in the memory cell section according to the information to be stored, and a contact hole 29 for forming a source electrode and a drain electrode is formed in the peripheral transistor section. Form.
（Ｅ）その後、ワードライン（又はビットライン）及び
周辺トランジスタ部の配線を形成するために金属層３０
、例えばＡｆｆ−３ｉ、を形成し、写真製版とエツチン
グによってパターン化する。(E) After that, a metal layer 30 is formed to form wiring for word lines (or bit lines) and peripheral transistor parts.
, for example, Aff-3i, and patterned by photolithography and etching.
ＰＮ接合部ではＰ型ポリシリコン層２３とＮ型ポリシリ
コン層２４は上下が逆になるように積層してもよい。At the PN junction, the P-type polysilicon layer 23 and the N-type polysilicon layer 24 may be stacked upside down.
第５図は他の実施例におけるメモリセル部を形成するプ
ロセスを示している。（ａ）から（ｅ）は第４図の（Ａ
）から（Ｅ）に対応している。FIG. 5 shows a process for forming a memory cell section in another embodiment. (a) to (e) are (A) in Figure 4.
) to (E).
第５図はフィールド酸化膜２１上に下層の金属層である
ビットライン（又はワードライン）を複数本配列するよ
うにしたものである。In FIG. 5, a plurality of bit lines (or word lines), which are the lower metal layer, are arranged on the field oxide film 21.
下層の金属層を形成するために、（ｂ）においてはフィ
ールド酸化膜２１上に例えばタングステン層を堆積し、
写真製版とエツチングによってパターン化して金属層２
２ａを形成する。In order to form the lower metal layer, in (b), for example, a tungsten layer is deposited on the field oxide film 21,
Metal layer 2 is patterned by photolithography and etching.
Form 2a.
その後、ＰＮ接合の形成１層間絶縁膜の形成。After that, a PN junction is formed and an interlayer insulating film is formed.
上層の金属層３０の形成は第４図と同様に行なう。The upper metal layer 30 is formed in the same manner as shown in FIG.
（効果）
本発明ではビットラインとワードラインの交点にＰ型半
導体層とＮ型半導体層を積層して形成してＰＮ接合を形
成し、記憶すべき情報に応じてコンタクトを形成したの
で、高集積度のメモリ装置を実現し、かつ、ビットライ
ンとワードラインをともに抵抗値の低い金属層として高
速読出しを可能にすることができる。(Effects) In the present invention, a P-type semiconductor layer and an N-type semiconductor layer are stacked and formed at the intersection of a bit line and a word line to form a PN junction, and contacts are formed according to the information to be stored. It is possible to realize a memory device with high integration density, and to enable high-speed reading by forming both bit lines and word lines as metal layers with low resistance values.
第１図は一実施例を示す平面図、第２図は第１図のＸ−
Ｘ線位置での断面図、第３図は一実施例を示す回路図、
第４図（Ａ）から同図（Ｅ）は一実施例を製造するプロ
セスを示す断面図、第５図（ａ）から（ｅ）は他の実施
例を製造するプロセスを示す断面図である。
２−１．２−２．４−１．４−２・・・・・・帯状金属
層。
３・・・・・・層間絶縁膜、
５・・・・・・Ｐ型ポリシリコン層。
６・・・・・・Ｎ型ポリシリコン層、
７・・・・・・コンタクト孔。Fig. 1 is a plan view showing one embodiment, and Fig. 2 is an X-
A cross-sectional view at the X-ray position, FIG. 3 is a circuit diagram showing one embodiment,
FIGS. 4(A) to 4(E) are cross-sectional views showing a process for manufacturing one embodiment, and FIGS. 5(a) to (e) are cross-sectional views showing a process for manufacturing another example. . 2-1.2-2.4-1.4-2... Band-shaped metal layer. 3... Interlayer insulating film, 5... P-type polysilicon layer. 6... N-type polysilicon layer, 7... Contact hole.
Claims (1)
状金属層の上部に絶縁膜を介して互いに平行に、かつ、
第１の帯状金属層と直交する方向に複数本の第２の帯状
金属層が設けられ、第１の帯状金属層と第２の帯状金属
層の交点には第１の帯状金属層と前記絶縁膜との間にＰ
型半導体層とＮ型半導体層が積層して形成されてＰＮ接
合が形成されており、第１の帯状金属層と第２の帯状金
属層の交点の前記絶縁膜には記憶すべき情報に応じてコ
ンタクト孔が形成されている半導体メモリ装置。on top of a plurality of first strip-shaped metal layers provided parallel to each other on the surface of the substrate, parallel to each other with an insulating film interposed therebetween;
A plurality of second band-shaped metal layers are provided in a direction perpendicular to the first band-shaped metal layer, and the first band-shaped metal layer and the insulating layer are provided at the intersections of the first band-shaped metal layer and the second band-shaped metal layer. P between the membrane
A PN junction is formed by stacking an N-type semiconductor layer and an N-type semiconductor layer, and the insulating film at the intersection of the first strip-shaped metal layer and the second strip-shaped metal layer is filled with a layer according to information to be stored. A semiconductor memory device in which a contact hole is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62335695A JPH01175765A (en) | 1987-12-29 | 1987-12-29 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62335695A JPH01175765A (en) | 1987-12-29 | 1987-12-29 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01175765A true JPH01175765A (en) | 1989-07-12 |
Family
ID=18291454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62335695A Pending JPH01175765A (en) | 1987-12-29 | 1987-12-29 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01175765A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5962903A (en) * | 1995-06-08 | 1999-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Planarized plug-diode mask ROM structure |
| CN104982885A (en) * | 2015-06-16 | 2015-10-21 | 江苏大学 | Method for preparing flavored flavor development base material with soy sauce residue as principal raw material |
-
1987
- 1987-12-29 JP JP62335695A patent/JPH01175765A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5962903A (en) * | 1995-06-08 | 1999-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Planarized plug-diode mask ROM structure |
| CN104982885A (en) * | 2015-06-16 | 2015-10-21 | 江苏大学 | Method for preparing flavored flavor development base material with soy sauce residue as principal raw material |
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