JPS5469393A - Production of semiconductor device - Google Patents
Production of semiconductor deviceInfo
- Publication number
- JPS5469393A JPS5469393A JP13716277A JP13716277A JPS5469393A JP S5469393 A JPS5469393 A JP S5469393A JP 13716277 A JP13716277 A JP 13716277A JP 13716277 A JP13716277 A JP 13716277A JP S5469393 A JPS5469393 A JP S5469393A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- groove
- wiring part
- metallic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
PURPOSE: To obtain a flat multilayer wiring without using liquid glass by separating a wiring metallic film into a wiring part and a non-wiring part by a groove and burying this groove with insulating materials.
CONSTITUTION: Polycrystal Si film 12 is grown in a vapour phase on Si substrate 11, and groove forming photo resistor pattern 13 to separate a metallic wiring from other metallic films is formed on film 12. Next, Al film 14 is evaporated throughout the surface, and pattern 13 is removed to generate Al wiring part 14', and a groove between film 14 and part 14' is etched to expose the surface of substrate 11. After that, PSG film 15 is grown throughout the surface to bury the groove with film 15, and an electrode contact window is opened on wiring part 14'. After that, the second-layer Al wiring 16 is evaporated from wiring part 14' to film 15, thereby giving a multilayer wiring structure. As a result, no cut is generated in the second-layer Al wiring, and a flat surface can be obtained.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13716277A JPS5469393A (en) | 1977-11-14 | 1977-11-14 | Production of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13716277A JPS5469393A (en) | 1977-11-14 | 1977-11-14 | Production of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5469393A true JPS5469393A (en) | 1979-06-04 |
Family
ID=15192260
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13716277A Pending JPS5469393A (en) | 1977-11-14 | 1977-11-14 | Production of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5469393A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5652465A (en) * | 1994-12-26 | 1997-07-29 | Fujitsu Limited | Semiconductor device having dummy patterns and an upper insulating layer having cavities |
US6099992A (en) * | 1994-12-12 | 2000-08-08 | Fujitsu Limited | Method for designing reticle, reticle, and method for manufacturing semiconductor device |
-
1977
- 1977-11-14 JP JP13716277A patent/JPS5469393A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6099992A (en) * | 1994-12-12 | 2000-08-08 | Fujitsu Limited | Method for designing reticle, reticle, and method for manufacturing semiconductor device |
US6553274B1 (en) | 1994-12-12 | 2003-04-22 | Fujitsu Limited | Method for designing reticle, reticle, and method for manufacturing semiconductor device |
US5652465A (en) * | 1994-12-26 | 1997-07-29 | Fujitsu Limited | Semiconductor device having dummy patterns and an upper insulating layer having cavities |
US5946557A (en) * | 1994-12-26 | 1999-08-31 | Fujitsu Ltd. | Method of manufacturing a semiconductor device having dummy patterns and an upper insulating layer having cavities |
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