JPS5443689A - Production of semiconductor integrated circuit unit - Google Patents

Production of semiconductor integrated circuit unit

Info

Publication number
JPS5443689A
JPS5443689A JP10988377A JP10988377A JPS5443689A JP S5443689 A JPS5443689 A JP S5443689A JP 10988377 A JP10988377 A JP 10988377A JP 10988377 A JP10988377 A JP 10988377A JP S5443689 A JPS5443689 A JP S5443689A
Authority
JP
Japan
Prior art keywords
layer
type
jfet
substrate
leading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10988377A
Other languages
Japanese (ja)
Other versions
JPS6138616B2 (en
Inventor
Kaoru Niino
Motofumi Masaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10988377A priority Critical patent/JPS5443689A/en
Publication of JPS5443689A publication Critical patent/JPS5443689A/en
Publication of JPS6138616B2 publication Critical patent/JPS6138616B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To form a bi-polar transistor and a JFET on he same substrate.
CONSTITUTION: An n+ type buried layer is formed on a p type Si substrate, and n- type epi-layer 4 is overlapped to form selectively P+ type ion injection layer 6. Layer 6 is stretched out by heat treatment, and p- type inversion layer 7 is formed while standing out from the substrate. Continuously, n type ions are injected to layer 7, and layer 7 is stretched out to form channel 9. Next, p- type isolation layer 10 is formed in n- type layer 3 in the upper part of the buried layer while surrounding p+ type base 10 and layer 9. Next, p+ type gate layer 17 is formed in layer 9, and an n+ type collector leading-out layer, emitter layer 14, source leading-out part 15 and drain leading-out part 16 are formed in layers 3 and 10. Finally, the Al electrode is added. Thus, an IC of the bi-polar. n channel JFET incorporating a JFET can be formed.
COPYRIGHT: (C)1979,JPO&Japio
JP10988377A 1977-09-14 1977-09-14 Production of semiconductor integrated circuit unit Granted JPS5443689A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10988377A JPS5443689A (en) 1977-09-14 1977-09-14 Production of semiconductor integrated circuit unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10988377A JPS5443689A (en) 1977-09-14 1977-09-14 Production of semiconductor integrated circuit unit

Publications (2)

Publication Number Publication Date
JPS5443689A true JPS5443689A (en) 1979-04-06
JPS6138616B2 JPS6138616B2 (en) 1986-08-30

Family

ID=14521569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10988377A Granted JPS5443689A (en) 1977-09-14 1977-09-14 Production of semiconductor integrated circuit unit

Country Status (1)

Country Link
JP (1) JPS5443689A (en)

Also Published As

Publication number Publication date
JPS6138616B2 (en) 1986-08-30

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