JPS54146583A - Semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a J-FET featuring the stable characteristics in an easy way by providing the p^- buried layer on the n⁺ buried layer on the p-type substrate to form the p-channel, using the n⁺ buried layer for the 1st gate layer and using the epitaxial layer on the p^- buried layer or the N⁺ layer on the surface of the epitaxial layer for the 2nd gate layer respectively.

CONSTITUTION: The n⁺ buried layer 103 is formed on the p-type substrate through the ion injection. Then the ion is injected again selectively to form p^- buried layer 104 and p-buried isolation layer 105, and n-epitaxial layer 102 is formed. Then p⁺ source layer 107, drain layer 108 and isolation layer 106 are formed selectively, and then ohmic contact n⁺ layer 110 is formed selectively for p⁺ source layer 107 for the 2nd gate and 1st gate layer 103. The opening is drilled to the insulator film on layers 107∼110 with the electrde attached. In such constitution, the p-channel can feature the p^- or p type, and the auto-doping is reduced at the epitaxial growing time with facilitated control of the specific resistance. Furthermore, no inversion is caused to n-layer 102 at the border between layer 102 and substrate 101. Thus, the high-accuracy and high-quality p^- buried layer can be formed in a stable way, ensuring a highly uniform control for the FET characteristics.

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