JPS57128073A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS57128073A
JPS57128073A JP20533081A JP20533081A JPS57128073A JP S57128073 A JPS57128073 A JP S57128073A JP 20533081 A JP20533081 A JP 20533081A JP 20533081 A JP20533081 A JP 20533081A JP S57128073 A JPS57128073 A JP S57128073A
Authority
JP
Japan
Prior art keywords
type
layer
regions
fet
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20533081A
Other languages
Japanese (ja)
Inventor
Toru Inaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP20533081A priority Critical patent/JPS57128073A/en
Publication of JPS57128073A publication Critical patent/JPS57128073A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248Combination of bipolar and field-effect technology

Abstract

PURPOSE:To easily perform the control of the channel width between gates for the subject device by a method wherein, when a J-FET and a bipolar transistor are provided on the same semiconductor substrate, the gate region of the FET is divided into a plurality of parts, and shallow source regions are provided in a contact state among the divided parts. CONSTITUTION:N<+> type impurities are separately on the surface of a P type Si substrate 11, an N type layer 33 is epitaxially grown on the whole surface including the above, and at the same time, the impurities deposited previously are diffused, and buried regions 32a and 32b are formed. Then, using the P<+> type region 34 which is penetrated to the substrate 11, the layer 33 is divided into two island type layers 33a and 33b, including regions 32a and 32b respectively, and the layer 33 is used for the J-FET and the layer 33b is used for the bipolar transistor 35c. Subsequently, P type gate regions 35a-35c are formed by diffusion leaving an interval among them, and shallow N<2> type source regions 36a and 36b are provided among the regions 35a-35c. Also, a P type base region is formed by diffusion in the layer 33a, and inside of which an N<+> type emitter region is provided.
JP20533081A 1981-12-21 1981-12-21 Semiconductor integrated circuit device Pending JPS57128073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20533081A JPS57128073A (en) 1981-12-21 1981-12-21 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20533081A JPS57128073A (en) 1981-12-21 1981-12-21 Semiconductor integrated circuit device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP48078335A Division JPS5843911B2 (en) 1973-07-13 1973-07-13 hand-held construction

Publications (1)

Publication Number Publication Date
JPS57128073A true JPS57128073A (en) 1982-08-09

Family

ID=16505134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20533081A Pending JPS57128073A (en) 1981-12-21 1981-12-21 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57128073A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04226061A (en) * 1988-06-27 1992-08-14 Texas Instr Inc <Ti> Process for formation of bipolar transistor and jfet transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04226061A (en) * 1988-06-27 1992-08-14 Texas Instr Inc <Ti> Process for formation of bipolar transistor and jfet transistor

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