JPS54144186A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54144186A
JPS54144186A JP5304278A JP5304278A JPS54144186A JP S54144186 A JPS54144186 A JP S54144186A JP 5304278 A JP5304278 A JP 5304278A JP 5304278 A JP5304278 A JP 5304278A JP S54144186 A JPS54144186 A JP S54144186A
Authority
JP
Japan
Prior art keywords
layer
distortion
layers
temperature gradient
held
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5304278A
Other languages
Japanese (ja)
Inventor
Takeomi Takase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5304278A priority Critical patent/JPS54144186A/en
Publication of JPS54144186A publication Critical patent/JPS54144186A/en
Pending legal-status Critical Current

Links

Landscapes

  • Thyristors (AREA)

Abstract

PURPOSE: To increase the electric performance such as dv/dt, by forming the high concentration layer in contact with the electrodes with thermal migration.
CONSTITUTION: GalB are simultaneously diffused on the both sides of the N type Si 11, the P layers 12,13 are made with no distortion, and N+ non-distortion layer 15 is made with diffusion between lattice. The SiO2 mask 14 is removed, the Al evaporation films 161 to 163 are selectively provided, the layer 161 is present in dot shape on the N+ layer 15, and the layer 162 is placed by surrounding the layer 163 in ring shape. The upper surface of the substrate is held at 690°C for 10 minutes at less than 10-5 Torr. and the lower side is held similarly. The migration of positive and negative is made, and the P+ layer 17 reaching the layer 12 through the layer 15 with Al is formed with positive temperature gradient, and Al is pushed back with inverse temperature gradient. After this process, the junction depth is X+P> X+N and the concentration is NP≈NN/10. Further, the Al layers 161 to 163 are removed, and the cathode electrode 19, gate auxiliary electrode 20 and anode electrode 21 are provided. With this method, the P+ layer 17 can accurately be formed, dv/dt effect can be increased, the device having high reliability can be obtained, and the process can be reduced.
COPYRIGHT: (C)1979,JPO&Japio
JP5304278A 1978-05-02 1978-05-02 Manufacture of semiconductor device Pending JPS54144186A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5304278A JPS54144186A (en) 1978-05-02 1978-05-02 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5304278A JPS54144186A (en) 1978-05-02 1978-05-02 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54144186A true JPS54144186A (en) 1979-11-10

Family

ID=12931820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5304278A Pending JPS54144186A (en) 1978-05-02 1978-05-02 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54144186A (en)

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