JPS5457955A - Production of semiconductor element - Google Patents

Production of semiconductor element

Info

Publication number
JPS5457955A
JPS5457955A JP12402577A JP12402577A JPS5457955A JP S5457955 A JPS5457955 A JP S5457955A JP 12402577 A JP12402577 A JP 12402577A JP 12402577 A JP12402577 A JP 12402577A JP S5457955 A JPS5457955 A JP S5457955A
Authority
JP
Japan
Prior art keywords
substrate
layer
ions
heated
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12402577A
Other languages
Japanese (ja)
Other versions
JPS6040697B2 (en
Inventor
Kuniaki Kumamaru
Shunichi Kai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12402577A priority Critical patent/JPS6040697B2/en
Publication of JPS5457955A publication Critical patent/JPS5457955A/en
Publication of JPS6040697B2 publication Critical patent/JPS6040697B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To improve an electrical characteristic by injecting H+ and H+ 2 ions to the interface between a Si substrate and a sticked layer or the substrate side and annealing them.
CONSTITUTION: BSG3 is laminated on SiO2 film 2 on a Si substrate after forming an aperture, and H+ and H+ 2 ions are injected to distribute them to the interface between the substrate and film 2 or the substrate side. Next, they are heated in a neutral atmosphere to form base layer 4. Next, apertures are formed selectively in films 3 and 2 to laminate PSG5, and the substrate is heated in a neutral atmosphere to form emitter layer 6 and collector connection layer 7. By this method, β becomes higher, and the leakage current is lowered with a high dielectric strength, so that the electrical characteristic can be improved
COPYRIGHT: (C)1979,JPO&Japio
JP12402577A 1977-10-18 1977-10-18 Method for manufacturing semiconductor devices Expired JPS6040697B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12402577A JPS6040697B2 (en) 1977-10-18 1977-10-18 Method for manufacturing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12402577A JPS6040697B2 (en) 1977-10-18 1977-10-18 Method for manufacturing semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5457955A true JPS5457955A (en) 1979-05-10
JPS6040697B2 JPS6040697B2 (en) 1985-09-12

Family

ID=14875158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12402577A Expired JPS6040697B2 (en) 1977-10-18 1977-10-18 Method for manufacturing semiconductor devices

Country Status (1)

Country Link
JP (1) JPS6040697B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663097A (en) * 1991-06-21 1997-09-02 Canon Kabushiki Kaisha Method of fabricating a semiconductor device having an insulating side wall

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663097A (en) * 1991-06-21 1997-09-02 Canon Kabushiki Kaisha Method of fabricating a semiconductor device having an insulating side wall

Also Published As

Publication number Publication date
JPS6040697B2 (en) 1985-09-12

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