JPS54139496A - Mos semiconductor load element - Google Patents

Mos semiconductor load element

Info

Publication number
JPS54139496A
JPS54139496A JP4654878A JP4654878A JPS54139496A JP S54139496 A JPS54139496 A JP S54139496A JP 4654878 A JP4654878 A JP 4654878A JP 4654878 A JP4654878 A JP 4654878A JP S54139496 A JPS54139496 A JP S54139496A
Authority
JP
Japan
Prior art keywords
terminal
resistance
region
gate
load element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4654878A
Other languages
Japanese (ja)
Inventor
Kenzo Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4654878A priority Critical patent/JPS54139496A/en
Publication of JPS54139496A publication Critical patent/JPS54139496A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0738—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with resistors only

Abstract

PURPOSE:To obtain the excellent constant current characteristics by connecting the drain to one of a pair of terminals and connecting the source to the other terminal via the gate and resistance means. CONSTITUTION:The MOS semiconductor load element is composed of the depression MOSFET element Q and resistance R, and drain D of element Q is connected to terminal T1 of one side. At the same time, source S is connected to terminal T2 of the other side via resistance R along with gate G also connected to T2. To obtain such load element, thick field insulator film 2 is provided at both end parts of N-type Si substrate 1, and P-type source and drain regions 5 and 6 are formed by diffusion within substrate 1 between films 2. In this case, region 5 is formed long in the lateral direction, part of which is used as resistance R. Then gate electrode 4 is coated between region 5 and 6 via gate insulator film 3, and region 5 including electrode 4 and resistance R is connected to terminal T2 with region 6 connected to terminal T1 each.
JP4654878A 1978-04-21 1978-04-21 Mos semiconductor load element Pending JPS54139496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4654878A JPS54139496A (en) 1978-04-21 1978-04-21 Mos semiconductor load element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4654878A JPS54139496A (en) 1978-04-21 1978-04-21 Mos semiconductor load element

Publications (1)

Publication Number Publication Date
JPS54139496A true JPS54139496A (en) 1979-10-29

Family

ID=12750358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4654878A Pending JPS54139496A (en) 1978-04-21 1978-04-21 Mos semiconductor load element

Country Status (1)

Country Link
JP (1) JPS54139496A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903111A (en) * 1983-12-06 1990-02-20 Fujitsu Limited Integrated circuit device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5332682A (en) * 1976-09-08 1978-03-28 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5332682A (en) * 1976-09-08 1978-03-28 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903111A (en) * 1983-12-06 1990-02-20 Fujitsu Limited Integrated circuit device

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