JPS54139495A - Manufacture of semiconductor memory - Google Patents

Manufacture of semiconductor memory

Info

Publication number
JPS54139495A
JPS54139495A JP4653178A JP4653178A JPS54139495A JP S54139495 A JPS54139495 A JP S54139495A JP 4653178 A JP4653178 A JP 4653178A JP 4653178 A JP4653178 A JP 4653178A JP S54139495 A JPS54139495 A JP S54139495A
Authority
JP
Japan
Prior art keywords
layer
film
opening
poly
crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4653178A
Other languages
Japanese (ja)
Inventor
Tatsu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4653178A priority Critical patent/JPS54139495A/en
Priority to US06/030,812 priority patent/US4239559A/en
Priority to DE19792916098 priority patent/DE2916098A1/en
Publication of JPS54139495A publication Critical patent/JPS54139495A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE: To ensure prescription of the gate length formed by the upper side with the pattern of the lower side by forming the inter-layer insulator film to be provided between the poly-crystal Si layers composed of the upper and lower sides with the material to which the impurity doped and then diffusing the impurity from the insulator film to the upper-side poly-crystal Si layer.
CONSTITUTION: Gate insulator film 2 composed of SiO2 and Si3N4 is coated on P-type Si substrate 1, and 1st poly-crystal Si layer 3 is stacked on the entire surface with covering by PSG film 4 which contains P of about 10 mol.%. Then wide opening 13 and narrow opening 14 are drilled on film 2, and opening 13 is covered with resist film 14. At the same time, P+-type isolation region 17 is formed by diffusion within substrate 1 within opening 14. After this, 2nd poly-crystal Si layer 5 is grown on the entire surface, and the impurities in film 4 are diffused into layer 5 through the heat treatment. In this case, impurities are diffused onto film 4 as well as to layer 5 within opening 14 but are not into opening 13, thus forming layer 19. In this way, the entire surface is covered with SiO2 film 20 with the opening provided to layer 19, and then prescribed N+-type data line 6 is formed by diffusion.
COPYRIGHT: (C)1979,JPO&Japio
JP4653178A 1978-04-21 1978-04-21 Manufacture of semiconductor memory Pending JPS54139495A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP4653178A JPS54139495A (en) 1978-04-21 1978-04-21 Manufacture of semiconductor memory
US06/030,812 US4239559A (en) 1978-04-21 1979-04-17 Method for fabricating a semiconductor device by controlled diffusion between adjacent layers
DE19792916098 DE2916098A1 (en) 1978-04-21 1979-04-20 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4653178A JPS54139495A (en) 1978-04-21 1978-04-21 Manufacture of semiconductor memory

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP59222164A Division JPS60143662A (en) 1984-10-24 1984-10-24 Manufacture of semiconductor device
JP59222165A Division JPS60143663A (en) 1984-10-24 1984-10-24 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS54139495A true JPS54139495A (en) 1979-10-29

Family

ID=12749860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4653178A Pending JPS54139495A (en) 1978-04-21 1978-04-21 Manufacture of semiconductor memory

Country Status (1)

Country Link
JP (1) JPS54139495A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764479A (en) * 1980-02-20 1988-08-16 Hitachi, Limited Semiconductor integrated circuit device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764479A (en) * 1980-02-20 1988-08-16 Hitachi, Limited Semiconductor integrated circuit device and method of manufacturing the same

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