JPS54111765A - Manufacture for semiconductor device - Google Patents
Manufacture for semiconductor deviceInfo
- Publication number
- JPS54111765A JPS54111765A JP1947678A JP1947678A JPS54111765A JP S54111765 A JPS54111765 A JP S54111765A JP 1947678 A JP1947678 A JP 1947678A JP 1947678 A JP1947678 A JP 1947678A JP S54111765 A JPS54111765 A JP S54111765A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- thick
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
Abstract
PURPOSE: To establish the device smaller in parasitic capacitance, by forming the metal wiring layer connecting the terminal connected to the back surface of the electrode of the semiconductor layer surface on the semiconductor substrate and the electrode thick before pelletizing.
CONSTITUTION: On the N type GaAs 2 on the semiinsulation GaAs substrate 1, the source, gate and drain electrodes 3 to 5 are provided in a given distance, and they are fixed on the glass plate 13 with wax 12. The back side of the substrate 1 is etched into about 50 μm thick, forming the Ti-Au film 14 and Au thick film 15. Further, the silica film 16 is selectively formed by taking the electrodes 3 to 5 as one unit, the mesa groove 17 reaching the film 14 is etched until the eaves reaches the end of the source electrode 3. The film 16 is photo etched, the opposite side of the electrode 4 is partly exposed, Ti gold film 18 is evaporated, forming the thick gold plating layer 19 up to the surface of the insulating film 16. Finally, the film 16 is removed, the layer 19 is cut off into pelletizing. With this constitution, the parasitic capacitance between the electrode on the semiconductor layer and the terminal of the metal layer of the back side of substrate can sufficiently be reduced, improving the high frequency performance.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1947678A JPS54111765A (en) | 1978-02-21 | 1978-02-21 | Manufacture for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1947678A JPS54111765A (en) | 1978-02-21 | 1978-02-21 | Manufacture for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54111765A true JPS54111765A (en) | 1979-09-01 |
Family
ID=12000376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1947678A Pending JPS54111765A (en) | 1978-02-21 | 1978-02-21 | Manufacture for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54111765A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63169036A (en) * | 1987-01-06 | 1988-07-13 | Nec Corp | Semiconductor device |
-
1978
- 1978-02-21 JP JP1947678A patent/JPS54111765A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63169036A (en) * | 1987-01-06 | 1988-07-13 | Nec Corp | Semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS54111765A (en) | Manufacture for semiconductor device | |
EP0208877A3 (en) | Method of manufacturing semiconductor devices having connecting areas | |
JPS6430272A (en) | Thin film transistor | |
JPS57191539A (en) | Semiconductor ion sensor | |
JPS6472567A (en) | Manufacture of semiconductor device | |
JPS5749252A (en) | Manufacture of semiconductor device | |
JPS5591134A (en) | Semiconductor device | |
JPS54138370A (en) | Flip chip mounting body | |
JPS5512766A (en) | Semiconductor device manufacturing method | |
JPS5291382A (en) | Insulating gate type field effect transistor | |
JPS55120170A (en) | Mos type semiconductor device | |
JPS57204175A (en) | Manufacture of semiconductor device | |
JPS57117280A (en) | Semiconductor device and manufacture thereof | |
JPS5727067A (en) | Manufacture of field-effect transistor | |
JPS57103358A (en) | Manufacture of amorphous silicon mosfet | |
JPS57153430A (en) | Manufacture of semiconductor device | |
JPS57211784A (en) | Field effect transistor | |
JPS5732655A (en) | Semiconductor integrated circuit device | |
JPS6417479A (en) | Manufacture of semiconductor device | |
JPS56165360A (en) | Manufacture of semiconductor device | |
JPS5683080A (en) | Schottky-barrier-diode | |
JPS5734368A (en) | Protective diode for insulated gate field-effect transistor | |
JPS5563880A (en) | Manufacturing method of semiconductor device | |
JPS6468729A (en) | Manufacture of thin film transistor | |
JPS6427273A (en) | Manufacture of vertical field effect transistor |