JPH11134242A5 - - Google Patents

Info

Publication number
JPH11134242A5
JPH11134242A5 JP1998248261A JP24826198A JPH11134242A5 JP H11134242 A5 JPH11134242 A5 JP H11134242A5 JP 1998248261 A JP1998248261 A JP 1998248261A JP 24826198 A JP24826198 A JP 24826198A JP H11134242 A5 JPH11134242 A5 JP H11134242A5
Authority
JP
Japan
Prior art keywords
data
buffer
memory means
repeat
data sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP1998248261A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11134242A (ja
Filing date
Publication date
Priority claimed from EP97115982A external-priority patent/EP0864977B1/en
Application filed filed Critical
Publication of JPH11134242A publication Critical patent/JPH11134242A/ja
Publication of JPH11134242A5 publication Critical patent/JPH11134242A5/ja
Ceased legal-status Critical Current

Links

JP10248261A 1997-09-13 1998-09-02 メモリ手段にアクセスするための装置 Ceased JPH11134242A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP97115982.7 1997-09-13
EP97115982A EP0864977B1 (en) 1997-09-13 1997-09-13 Memory latency compensation

Publications (2)

Publication Number Publication Date
JPH11134242A JPH11134242A (ja) 1999-05-21
JPH11134242A5 true JPH11134242A5 (https=) 2005-11-04

Family

ID=8227349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10248261A Ceased JPH11134242A (ja) 1997-09-13 1998-09-02 メモリ手段にアクセスするための装置

Country Status (4)

Country Link
US (1) US6351793B2 (https=)
EP (1) EP0864977B1 (https=)
JP (1) JPH11134242A (https=)
DE (1) DE69700328T2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2829253A1 (fr) * 2001-08-31 2003-03-07 Koninkl Philips Electronics Nv Controle d'acces dynamique d'une fonction a ressource collective
DE10159165B4 (de) * 2001-12-03 2007-02-08 Agilent Technologies, Inc. (n.d.Ges.d.Staates Delaware), Palo Alto Vorrichtung zum Messen und/oder Kalibrieren eines Testkopfes
DE60131067T2 (de) 2001-12-05 2008-05-15 Verigy (Singapore) Pte. Ltd. Leitungsentzerrer zur Kompensation von Droop-Effekten
EP1351067B1 (en) 2003-02-25 2004-11-10 Agilent Technologies Inc Transition tracking
US7104346B2 (en) * 2003-03-25 2006-09-12 Schaffner Walter E Power wheelchair
DE60308844T2 (de) 2003-06-17 2007-03-01 Agilent Technologies, Inc., Palo Alto Sigma-Delta-Modulator mit Pulsbreitenmodulations-Ausgang
EP1600784A1 (en) 2004-05-03 2005-11-30 Agilent Technologies, Inc. Serial/parallel interface for an integrated circuit
EP1610204B1 (en) 2004-06-24 2008-10-29 Verigy (Singapore) Pte. Ltd. Fast synchronization of a number of digital clocks
EP1610137B1 (en) 2004-06-24 2009-05-20 Verigy (Singapore) Pte. Ltd. Per-pin clock synthesis
WO2006002693A1 (en) 2004-07-07 2006-01-12 Agilent Technologies, Inc. Evaluation of an output signal of a device under test
EP1624577B1 (en) 2004-08-06 2008-07-23 Verigy (Singapore) Pte. Ltd. Improved analog signal generation using a delta-sigma modulator
WO2006092173A1 (en) 2005-03-02 2006-09-08 Agilent Technologies, Inc. Analog signal test using a-priori information
EP1701173B1 (en) 2005-03-11 2008-08-20 Verigy (Singapore) Pte. Ltd. Error detection in compressed data
WO2006117255A1 (en) 2005-04-29 2006-11-09 Verigy (Singapore) Pte Ltd. Communication circuit for a bi-directonal data transmission
US8838406B2 (en) 2008-11-11 2014-09-16 Advantest (Singapore) Pte Ltd Re-configurable test circuit, method for operating an automated test equipment, apparatus, method and computer program for setting up an automated test equipment
JP5873275B2 (ja) * 2011-09-12 2016-03-01 キヤノン株式会社 描画装置及び物品の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5847741B2 (ja) * 1978-03-29 1983-10-24 日本電信電話株式会社 パタ−ン発生器
CA1251575A (en) * 1985-12-18 1989-03-21 A. Keith Jeffrey Automatic test system having a "true tester-per-pin" architecture
US5317718A (en) * 1990-03-27 1994-05-31 Digital Equipment Corporation Data processing system and method with prefetch buffers
JPH07253922A (ja) * 1994-03-14 1995-10-03 Texas Instr Japan Ltd アドレス生成回路
US5890219A (en) * 1996-11-27 1999-03-30 Emc Corporation Redundant writing of data to cached storage system
US5890207A (en) * 1996-11-27 1999-03-30 Emc Corporation High performance integrated cached storage device
US6112266A (en) * 1998-01-22 2000-08-29 Pc-Tel, Inc. Host signal processing modem using a software circular buffer in system memory and direct transfers of samples to maintain a communication signal

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