JPH10189961A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, and a manufacturing method therefor, in which a parasitic MOS transistor does not turn on, even when an LOCOS oxide is thin. SOLUTION: N+-type drain and source regions 4, 5 are formed, while being spaced apart from each other, in a p-type well region 3, such that they are exposed to the surface thereof and an insulation gate 7 is formed on the p-type well region 3 through an oxide 6 between the n+-type drain and source regions 4, 5. The n+-type drain and source regions 4, 5 constitute an NMOS transistor along with the insulation gate 7. An LOCOS oxide 10 is deposited between adjacent NMOS transistors and a p+-type impurity region 11 is formed beneath the LOCOS oxide 10. A polysilicon 12 connected electrically with 0V is deposited on the LOCOS oxide 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an NMOS transistor.

[0002]

2. Description of the Related Art FIG. 7 is a schematic sectional view showing an NMOS transistor according to a conventional example. The conventional NMOS transistor has a p-type semiconductor substrate 1 and an n-type epitaxial layer 2 formed on the p-type semiconductor substrate 1. Further, a p-type well region 3 is formed in the n-type epitaxial layer 2 so as to be exposed at the surface of the n-type epitaxial layer 2, and the p-type well region 3 is exposed so as to be exposed at the surface of the p-type well region 3.
An n + type drain region 4 and an n + type source region 5 are formed spaced apart from each other.

Further, an insulating gate 7 made of polysilicon or the like is formed on a p-type well region 3 interposed between an n + -type drain region 4 and an n + -type source region 5 with an oxide film 6 interposed therebetween. A gate electrode (not shown) made of aluminum (Al) or the like so as to be electrically connected to the gate 7.
Are formed.

A drain electrode 8 made of aluminum (Al) or the like is formed so as to be electrically connected to n + type drain region 4, and aluminum (Al) is formed so as to be electrically connected to n + type source region 5. ) Etc. are formed. Then, the N + type drain region 4, the n + type source region 5 and the insulated gate 7 make the NMO
This constitutes an S transistor.

A LOCOS oxide film 10 is formed in the p-type well region 3 so as to be exposed on the surface of the p-type well region 3 interposed between adjacent NMOS transistors.
In the p-type well region 3 below the LOCOS oxide film 10, a p + -type impurity region 11 as a channel stopper is formed.
Are formed.

Hereinafter, a manufacturing process of a conventional NMOS transistor will be described with reference to the drawings. FIG. 8 is a schematic cross-sectional view showing a former stage of a manufacturing process of an NMOS transistor according to a conventional example, and FIG. First, an n-type epitaxial layer 2 is formed on a semiconductor substrate 1, an oxide film 14 is formed on the n-type epitaxial layer 2 by thermal oxidation or the like (FIG. 8A), and photolithography and etching techniques are used. The opening 14a is formed by patterning into a predetermined shape.

Subsequently, a p-type impurity such as boron (B) is ion-implanted into the n-type epitaxial layer 2 by using the oxide film 14 in which the opening 14a is formed as a mask. 3 (FIG. 8)
(B)). The oxide film 14 is buried in the opening 14a by the oxidation at this time.

Next, a photoresist is applied on the oxide film 14, exposed and developed to be patterned into a predetermined shape, and the patterned photoresist is used as a mask (hereinafter, referred to as PB mask 15). ,
The opening 14b is formed by etching the oxide film 14.
Then, p-type impurities such as boron (B) are ion-implanted from the opening 14b (FIG. 8C), the PB mask 15 is removed by plasma ashing or the like, and the oxide film 14 is removed by etching. The region into which the p-type impurity is ion-implanted becomes the p + -type impurity region 11 due to the subsequent heat process.

Next, an oxide film 16 is formed on the n-type epitaxial layer 2 in which the p-type well region 3 is formed near the surface by thermal oxidation or the like, and silane (SiH
4) and ammonia (NH3) as source gas
The silicon nitride film 17 is formed by the D method, and the silicon nitride film 17 is dry-etched using a photoresist (not shown) patterned in a predetermined shape as a mask (this mask is hereinafter referred to as an OD mask). ,
The silicon nitride film 17 is selectively removed to form an opening 17a.

Next, using the silicon nitride film 17 in which the opening 17a is formed as a mask, LOCOS (Locol Oxidati
on of silicon) to form the LOCOS oxide film 10 (FIG. 8D), and the silicon nitride film 15 is removed by etching. In this heat step, the region into which the ions are implanted in FIG. 8C is diffused to form the p + type impurity region 11 as a channel stopper.

Next, after the oxide film 16 is removed by etching, an oxide film 6 (this oxide film becomes a gate oxide film) is formed by dry oxidation or the like, and the oxide film 6 and LOCOS are formed.
Polysilicon is deposited on the oxide film 10 by using a low pressure CVD method, and the polysilicon is selectively removed by using a photolithography technique and an etching technique to form an insulated gate 7 made of polysilicon (FIG. 8 ( e)).

Next, the oxide film 6, the insulated gate 7 and the LOC
A photoresist 20 is applied on the OS oxide film 10, and is patterned into a predetermined shape by performing exposure and development.
Using the patterned photoresist 20 as a mask, an n-type impurity such as phosphorus (P) is ion-implanted (FIG. 8).
(F)), the n + type drain region 4 and n +
A mold source region 5 is formed (FIG. 9A).

Next, an NSG as an interlayer insulating film is formed on the entire surface of the n-type epitaxial layer 2 on the side where the insulating gate 7 is formed.
/ BPSG or the like oxide film 6 is formed (FIG. 9B), n +
N + type drain region 4, n for making contact with the type drain region 4, n + type source region 5 and insulated gate 7.
The oxide film 6 at a desired position on the + source region 5 and the insulating gate 7 is removed by etching to form an opening 6a (FIG. 9C).

Next, a drain electrode 8, a source electrode 9, and a gate electrode (not shown) made of aluminum or the like are formed so as to fill the opening 6a (FIG. 9 (d)). A passivation film (not shown) such as NSG / PSG is formed by a normal pressure CVD method on the entire surface of the layer 2 on which the insulating gate 7 is formed to form an NMOS transistor.

As an example of a method of forming the drain electrode 8, the source electrode 9, and the gate electrode, an aluminum layer is formed by sputtering using aluminum (Al) as a target, and photolithography and etching techniques are used. There is a method of forming by patterning into a predetermined shape by using.

In the conventional NMOS transistor, when a voltage higher than the threshold value is applied to the gate electrode, a channel is formed on the surface of the channel region below the insulated gate 7, and the channel is formed between the n + type drain region 4 and the n + type source region 5. Current flows through.

Further, in the p-type well region 3, a plurality of N
MOS transistor is formed, one of the NMOS
N + type source region 5 of the transistor and adjacent NMO
Parasitic M between the n + type drain region 4 of the S transistor
It constitutes an OS transistor.

This parasitic MOS transistor is LOCO
The wiring having a positive potential on the S oxide film 10
The p + -type impurity region 11 under the S oxide film 10 is inverted to the n-type to be in a conducting state, and a leak current flows between adjacent NMOS transistors.

Therefore, p + under the LOCOS oxide film 10
It is necessary to increase the concentration of the mold impurity region 11, that is, to form a channel stopper so that the parasitic MOS transistor does not turn on.

The main factors that determine the source-drain breakdown voltage of the NMOS transistor are the p + type impurity region 11 and n
It is the distance from the + type drain region 4.

That is, when a voltage is applied to the drain electrode 8, a depletion layer extends from the n + type drain region 4 to the p + type impurity region 11, and a breakdown occurs between the n + type drain region 4 and the p + type impurity region 11. The voltage at that time becomes the breakdown voltage between the source and the drain.

Therefore, the larger the distance between the p + type impurity region 11 and the n + type drain region 4, the higher the breakdown voltage can be stably obtained.

[0023]

However, the conventional NM
In the OS transistor, if an element is designed by widening the distance between the p + type impurity region 11 and the n + type drain region 4, the element size becomes large and the cost becomes high. Therefore, the OS transistor is designed as narrow as possible.

In the case of a conventional NMOS transistor, p +
The distance between the p-type impurity region 11 and the n + -type drain region 4 is two, such that the p + -type impurity region 11 is the PB mask 13 and the n + -type drain region 4 is the end of the LOCOS oxide film 10 formed by the OD mask. Is determined by the mask.

That is, the alignment accuracy of the two masks, p +
The distance between the p + type impurity region 11 and the n + type drain region 4 is determined by the etching precision for forming the type impurity region 11, and the distance between the p + type impurity region 11 and the n + type drain region 4. It has been difficult to stably obtain a source-drain breakdown voltage.

The LOCOS oxide film 10 has a parasitic MO
In order to make the S transistor difficult to turn on, a certain film thickness is required, and in this case, it is formed by a high-temperature heat treatment.

However, due to the high-temperature LOCOS oxidation process, the p-type impurity in the p + -type impurity region 11 also diffuses in the lateral direction, and the p + -type impurity region 11 and the n + -type drain region 4
There is a problem that the distance between the source and the drain becomes smaller and the breakdown voltage between the source and the drain becomes lower.

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device in which a parasitic MOS transistor does not turn on even when the LOCOS oxide film is thin, and a semiconductor device thereof. It is to provide a manufacturing method.

[0029]

According to the first aspect of the present invention,
A first conductivity type semiconductor substrate, a second conductivity type epitaxial layer formed on one main surface of the semiconductor substrate, and a first conductivity type formed in the epitaxial layer so as to be exposed on the surface of the epitaxial layer. A conductive type well region, a high concentration second conductivity type drain region and a high concentration second conductivity type source region formed separately in the well region so as to be exposed on the surface of the well region; An insulating gate formed on the well region interposed between the drain region and the source region via an oxide film, and adjacent to the drain region of the MOS transistor including the drain region, the source region, and the insulating gate; LOCOS formed in the well region so as to be exposed on the surface of the well region interposed between the source region of the other MOS transistor And monolayer, in a semiconductor device comprising and a lower portion of the well region a high concentration first conductivity type impurity region formed in the LOCOS oxide film, the L
Polysilicon is formed on an OCOS oxide film, and the polysilicon is electrically connected to 0V.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the LOCOS oxide film is divided on the surface of the well region, and exposed on the surface of the well region between the divided LOCOS oxide films. Thus, the impurity region is formed in the well region, and the polysilicon and the impurity region are electrically connected.

According to a third aspect of the present invention, an epitaxial layer of the second conductivity type is formed on a semiconductor substrate of the first conductivity type, and the first conductivity type is formed in the epitaxial layer so as to be exposed on the surface of the epitaxial layer. Forming a well region of the well region, forming a LOCOS oxide film in the well region so as to be exposed on the surface of the well region, and using the LOCOS oxide film as a mask to interpose the wells between the LOCOS oxide films. Forming a high-concentration first conductivity type impurity region in the well region so as to be exposed on the surface of the region; forming polysilicon on the impurity region so as to be electrically connected to the impurity region; Forming an insulating gate on the epitaxial layer via an oxide film, and ion-implanting a second conductivity type impurity using the LOCOS oxide film and the insulating gate as a mask; A high concentration second conductivity type drain region and a high concentration second conductivity type source region are formed separately in the well region so as to be exposed on the surface of the well region, and the polysilicon is electrically set to 0V. It is characterized by being connected.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 = In this embodiment, the first conductivity type is described as p-type and the second conductivity type is described as n-type. However, the present invention is not limited to this, and the first conductivity type is n-type. Alternatively, the second conductivity type may be p-type. The basic configuration of the NMOS transistor according to the present embodiment is the same as that of the NMOS transistor shown in FIG. 4 as a conventional example, and therefore, the same portions are denoted by the same reference numerals and description thereof will be omitted. FIG. 1 shows an NM according to an embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view illustrating an OS transistor. The NMOS transistor according to the present embodiment is the same as the NMOS transistor shown in FIG.
Polysilicon 12 is formed thereon, and
It is electrically connected to the potential of V and is polysilicon 1
2 and the oxide film 6 are formed with an interlayer insulating film 13 such as TEOS, and the LOCOS oxide film 10 is an NM shown in the conventional example.
The configuration is such that it is thinner than the LOCOS oxide film 10 of the OS transistor. Incidentally, in FIG.
A connection portion for electrically connecting to the potential of V is not shown.
As an example of a method of electrically connecting the polysilicon 12 to a potential of 0 V, there is a method of removing an oxide film 6 at an arbitrary position on the polysilicon 12 and performing wiring of aluminum (Al) or the like.

The manufacturing process of the NMOS transistor according to this embodiment will be described below with reference to the drawings. FIG.
FIG. 3 is a schematic cross-sectional view showing a stage before the manufacturing process of the NMOS transistor according to the present embodiment, and FIG. 3 is a schematic cross-sectional view showing a stage after the manufacturing process of the NMOS transistor according to the embodiment. Since the manufacturing process of the NMOS transistor according to the present embodiment up to FIG. 2C is the same as the manufacturing process up to FIG. 8C shown as a conventional example, the description thereof is omitted here. The process of d) will be described.

PB mask 1 by plasma ashing or the like
5 is removed, and the oxide film 14 is removed by etching.
The region into which the p-type impurity is ion-implanted becomes the p + -type impurity region 11 due to the subsequent heat process.

Next, an oxide film 16 is formed on the n-type epitaxial layer 2 in which the p-type well region 3 is formed near the surface by thermal oxidation or the like, and silane (SiH
4) and ammonia (NH3) as source gas
A silicon nitride film 17 is formed by the D method, and the silicon nitride film 17 is dry-etched by using a photoresist (not shown) patterned in a predetermined shape as a mask to selectively remove the silicon nitride film 17. To form the opening 17a.

Next, using the silicon nitride film 17 having the opening 17a as a mask, LOCOS (Locol Oxidati
on of silicon) to form the LOCOS oxide film 10 (FIG. 2D), and the silicon nitride film 17 is removed by etching. In this heat step, the region into which the ions are implanted in FIG. 2C is diffused, and becomes the p + -type impurity region 11 as a channel stopper.
The LOCOS oxide film 10 according to the present embodiment is the same as the LOCOS oxide film 10 of the NMOS transistor shown in the conventional example.
It is formed to be thinner than that.

Next, the oxide film 1 of the n-type epitaxial layer 2
LOC is formed by forming a polysilicon 12 on the entire surface on which 6 is formed using a low pressure CVD method, applying a photoresist 18 on the polysilicon 12, exposing and developing the same.
The photoresist 18 is removed only on the OS oxide film 10 and the other portions of the photoresist 18 are removed, and etching is performed using the photoresist 18 as a mask.
Polysilicon 12 is formed only on the OS oxide film 10 (FIG. 2E), and the photoresist 18 is removed by plasma ashing or the like.

Next, an interlayer insulating film 13 of TEOS or the like is formed by CVD on the entire surface of the n-type epitaxial layer 2 on which the polysilicon 12 is formed, and a photoresist 19 is applied on the interlayer insulating film 13. Then, by exposing and developing, the photoresist 19 is formed only on the LOCOS oxide film 10.
The photoresist 19 is removed from the remaining portions, and the interlayer insulating film 13 is etched using the photoresist 19 as a mask, thereby forming the interlayer insulating film 13 on the side and upper surfaces of the polysilicon 12 (FIG. 2 ( f)), the photoresist 19 is removed by plasma ashing or the like. At this time, the oxide film 16 is also removed by etching.

Next, an oxide film 6 (this oxide film becomes a gate oxide film) is formed on the p-type well region 3 by dry oxidation or the like, and a reduced pressure C is applied on the oxide film 6 and the LOCOS oxide film 10.
Polysilicon is deposited using the VD method, and the polysilicon is selectively removed using the photolithography technique and the etching technique to form the insulated gate 7 made of polysilicon (FIG. 3A).

Next, a photoresist 20 is applied on the oxide film 6, the insulating gate 7 and the interlayer insulating film 13 and exposed and developed to leave the photoresist 20 only on the insulated gate 7 and leave another photoresist. The photoresist 20 at the location is removed, n-type impurities such as phosphorus (P) are ion-implanted using the photoresist 20 as a mask (FIG. 3B), and the photoresist 20 is removed by plasma ashing or the like. An n + type drain region 4 and an n + type source region 5 are formed (FIG. 3C). The n-type impurity implantation region is determined by the end of the LOCOS oxide film 10 and the end of the insulated gate 7.

The manufacturing steps shown in FIGS. 3D to 3F are the same as the manufacturing steps shown in FIGS. 9B to 9D shown as a conventional example, so that the description is omitted here. .

Therefore, in this embodiment, since the polysilicon 12 grounded to 0V is formed on the LOCOS oxide film 10, the parasitic MOS transistor is turned on even if the thin LOCOS oxide film 10 is formed. Without
Further, since the LOCOS oxide film 10 is thin, the high temperature heat treatment can be performed in a short time, the lateral diffusion of the p-type impurity in the p + -type impurity region 11 can be suppressed, and the p + -type impurity region 1 can be suppressed.
The distance between 1 and the n + type drain region 4 is also kept constant, and the source-drain breakdown voltage does not decrease.

Second Embodiment In the present embodiment, the first conductivity type is p-type and the second conductivity type is n-type. However, the first conductivity type is not limited to this, and the first conductivity type is n-type. Alternatively, the second conductivity type may be p-type. The basic configuration of the NMOS transistor according to the present embodiment is the same as that of the NMOS transistor shown in FIG. 1 as the first embodiment, and therefore, the same portions will be denoted by the same reference numerals and description thereof will be omitted. FIG. 4 is a schematic sectional view showing an NMOS transistor according to another embodiment of the present invention. The NMOS transistor according to the present embodiment is the same as the NMOS transistor shown in FIG.
Two LOCOS oxide films 10 are formed between the MOS transistors, and ap + -type impurity region 11 is formed in the p-type well region 3 so as to be exposed on the surface of the p-type well region 3 interposed between the two LOCOS oxide films 10. And the p + type impurity region 1
This is a configuration in which a polysilicon 12 is formed so as to be electrically connected to the polysilicon 1.

Hereinafter, the manufacturing process of the NMOS transistor according to this embodiment will be described with reference to the drawings. FIG.
Is a schematic cross-sectional view showing a stage before the manufacturing process of the NMOS transistor according to the present embodiment, and FIG. 6 is a schematic cross-sectional view showing a stage after the manufacturing process of the NMOS transistor according to the embodiment. Since the manufacturing process of the NMOS transistor according to the present embodiment up to FIG. 5B is the same as the manufacturing process up to FIG. 8B shown as a conventional example, the description thereof is omitted here. The process will be described from step c).

After removing the oxide film 14 by etching, an oxide film 16 is formed on the n-type epitaxial layer 2 in which the p-type well region 3 is formed near the surface by thermal oxidation or the like, and silane is formed on the oxide film 16. A silicon nitride film 17 is formed by a low pressure CVD method using (SiH4) and ammonia (NH3) as source gases, and the silicon nitride film 17 is dry-etched using a photoresist (not shown) patterned into a predetermined shape as a mask. Thereby, the silicon nitride film 17 is selectively removed to form the opening 17a. At this time, the silicon nitride film 17 has the n + type drain region 4, the n + type source region 5, the insulated gate 7, and the p +
It is formed on the location where the type impurity region 11 is formed.

Then, the LOCOS oxide film 10 is formed by performing LOCOS oxidation using the silicon nitride film 17 having the opening 17a as a mask (FIG. 5C), and the silicon nitride film 17 is removed by etching. . In addition,
The LOCOS oxide film 10 according to the present embodiment is formed to be thinner than the LOCOS oxide film 10 of the NMOS transistor shown in the conventional example.

Next, the oxide film 16 and the LOCOS oxide film 1
0 is coated with a photoresist, exposed and developed to be patterned into a predetermined shape, and p-type impurities such as boron are ion-implanted using the patterned photoresist as a mask (PB mask 15) (see FIG. )), The PB mask 15 is removed by plasma ashing or the like, and annealing is performed to form the p + type impurity region 11. At this time, the region into which the p-type impurity is ion-implanted is two LOs.
It is determined by the edge of the COS oxide film 10.

Next, after removing the oxide film 16 by etching, polysilicon is deposited on the entire surface of the etched surface of the n-type epitaxial layer 2 by using a low pressure CVD method, and photolithography and etching are used. The polysilicon is selectively removed by removing the polysilicon 1 only on the LOCOS oxide film 10 and the p + type impurity region 11.
2 is formed (FIG. 5E).

Next, the entire surface of the n-type epitaxial layer 2 on which the polysilicon 12 is formed is subjected to TE by a CVD method.
An interlayer insulating film 13 such as an OS is formed, a photoresist 19 is applied on the interlayer insulating film 13, and exposure and development are performed to leave the photoresist 19 only on the LOCOS oxide film 10 and the p + type impurity region 11. Then, the photoresist 19 in other places is removed. Then, the photoresist 19
The interlayer insulating film 13 is etched by using the mask as a mask to leave the interlayer insulating film 13 only on the upper surface and the side surface of the polysilicon 12 and remove the interlayer insulating film 13 at other portions (FIG. 5F). The photoresist 19 is removed by ashing or the like.

The manufacturing steps shown in FIGS. 6A to 6F are the same as the manufacturing steps shown in FIGS. 3A to 3F shown in the first embodiment, and the description is omitted here. To do.

Therefore, in this embodiment, since the polysilicon 12 grounded to 0V is formed so as to be electrically connected to the p + type impurity region 11, the LO having a small film thickness is formed.
Even when the COS oxide film 10 is formed, the parasitic MOS transistor is not turned on, and the LOCOS oxide film 10 is thin, so that a high-temperature heat treatment can be performed in a short time, and the p-type impurity region 11 has a p-type impurity. Is also suppressed in the lateral direction, the distance between the p + -type impurity region 11 and the n + -type drain region 4 is kept constant, and the source-drain breakdown voltage does not decrease.

Since the formation region of the p + type impurity region 11 is determined by the end of the LOCOS oxide film 10 and the formation region of the n + type drain region 4 is also determined by the end of the LOCOS oxide film 10, the p + type impurity region 11 and the n + type drain The distance from the region 4 does not vary, and a stable breakdown voltage can be obtained.

[0054]

According to the first aspect of the present invention, a semiconductor substrate of the first conductivity type, an epitaxial layer of the second conductivity type formed on one main surface of the semiconductor substrate, and a semiconductor substrate exposed on the surface of the epitaxial layer. A first conductivity type well region formed in the epitaxial layer, a high concentration second conductivity type drain region formed in the well region so as to be exposed on a surface of the well region, and a high concentration second region. A conductive type source region, an insulating gate formed on the well region interposed between the drain region and the source region via an oxide film, and a drain region of a MOS transistor including the drain region, the source region and the insulating gate LOCOS formed in the well region so as to be exposed at the surface of the well region interposed between the source region of another adjacent MOS transistor.
In a semiconductor device having an oxide film and a high-concentration first-conductivity-type impurity region formed in a well region below a LOCOS oxide film, polysilicon is formed on the LOCOS oxide film, and polysilicon is formed. Since it is electrically connected to 0 V, even if a thin LOCOS oxide film is formed,
The S transistor does not turn on and the LOCO
Since the thickness of the S oxide film is thin, high-temperature heat treatment is completed in a short time, diffusion of impurities in the lateral direction is suppressed, the distance between the impurity region and the drain region is kept constant, and the source -It was possible to provide a semiconductor device capable of obtaining a withstand voltage between drains.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the LOCOS oxide film is divided into two at the surface of the well region, and is exposed on the surface of the well region between the divided LOCOS oxide films. Since the impurity region is formed in the well region and the polysilicon and the impurity region are electrically connected to each other, the impurity region is formed in two LO regions.
Determined by the end of the COS oxide film, the formation region of the drain region is also L
This is determined by the end of the OCOS oxide film, the distance between the impurity region and the drain region becomes constant, and a more stable source-drain breakdown voltage can be obtained.

According to a third aspect of the present invention, a second conductivity type epitaxial layer is formed on a first conductivity type semiconductor substrate, and a first conductivity type well is formed in the epitaxial layer so as to be exposed on the surface of the epitaxial layer. A region is formed and two LOCOSs are formed in the well region so as to be exposed on the surface of the well region.
An oxide film is formed at a distance, and a high-concentration first conductivity type impurity region is formed in the well region using the LOCOS oxide film as a mask so as to be exposed on the surface of the well region interposed between the LOCOS oxide films. Forming polysilicon so as to be electrically connected to the impurity region on the region, forming an insulating gate via an oxide film on the epitaxial layer,
The second conductive type impurity is ion-implanted by using the OS oxide film and the insulating gate as a mask, and is separated into the well region so as to be exposed on the surface of the well region. Since the conductive type source region is formed and the polysilicon is electrically connected to 0 V, the parasitic MOS transistor does not turn on even if a thin LOCOS oxide film is formed, and the LOCOS oxide film is formed. Since the thickness is small, high-temperature heat treatment can be performed in a short time, the diffusion of impurities in the lateral direction is suppressed, the formation region of the impurity region is determined by the two LOCOS oxide film edges, and the formation region of the drain region is also LOCOS oxide. Production of a semiconductor device in which the distance between the impurity region and the drain region is determined by the end of the film and the source-drain breakdown voltage can be stably obtained. It is possible to provide a law.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing an NMOS transistor according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a first stage of a manufacturing process of the NMOS transistor according to the embodiment.

FIG. 3 is a schematic cross-sectional view showing a latter stage of a manufacturing process of the NMOS transistor according to the embodiment.

FIG. 4 is a schematic sectional view showing an NMOS transistor according to another embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a first stage of a manufacturing process of the NMOS transistor according to the embodiment.

FIG. 6 is a schematic cross-sectional view showing a latter stage of a manufacturing process of the NMOS transistor according to the embodiment.

FIG. 7 is a schematic sectional view showing an NMOS transistor according to a conventional example.

FIG. 8 is a schematic cross-sectional view showing a first stage of a manufacturing process of an NMOS transistor according to a conventional example.

FIG. 9 is a schematic cross-sectional view showing a latter stage of a manufacturing process of an NMOS transistor according to a conventional example.

[Explanation of symbols]

 1 p-type semiconductor substrate 2 n-type epitaxial layer 3 p-type well region 4 n + type drain region 5 n + type source region 6 oxide film 6a opening 7 insulating gate 8 drain electrode 9 source electrode 10 LOCOS oxide film 11 p + type impurity region 12 Oxide film 12a, 12b Opening 13 PB mask 14 Oxide film 15 Silicon nitride film 15a Opening 16 Photoresist 16a Opening 17 Photoresist

 ───────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Nagahama 1048 Kazumasa Kadoma, Osaka Pref. Matsushita Electric Works, Ltd.

Claims (3)

[Claims] 1. A first-conductivity-type semiconductor substrate, a second-conductivity-type epitaxial layer formed on one main surface of the semiconductor substrate, and an epitaxial layer within the epitaxial layer so as to be exposed at the surface of the epitaxial layer. The formed first conductivity type well region, a high concentration second conductivity type drain region and a high concentration second conductivity type drain region formed separately in the well region so as to be exposed on the surface of the well region. A source region, an insulating gate formed on the well region interposed between the drain region and the source region via an oxide film, and an M including the drain region, the source region, and the insulating gate.
The M adjacent to the drain region of the OS transistor
A LOCOS oxide film formed in the well region so as to be exposed at the surface of the well region interposed between the source region of the OS transistor and the well region below the LOCOS oxide film. In a semiconductor device having a high-concentration first conductivity type impurity region,
A semiconductor device, wherein polysilicon is formed on the LOCOS oxide film, and the polysilicon is electrically connected to 0V. 2. The method according to claim 1, wherein the LOCOS oxide film is divided on a surface of the well region, and the impurity region is formed in the well region so as to be exposed on a surface of the well region between the divided LOCOS oxide films. 2. The semiconductor device according to claim 1, wherein polysilicon and the impurity region are electrically connected. 3. An epitaxial layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, and a well region of the first conductivity type is formed in the epitaxial layer so as to be exposed on a surface of the epitaxial layer. Forming two LOCOS oxide films in the well region so as to be exposed on the surface of the well region, and using the LOCOS oxide film as a mask;
A high-concentration first conductivity type impurity region is formed in the well region so as to be exposed at the surface of the well region interposed between the LOCOS oxide films, and the impurity region is electrically connected to the impurity region. To form an insulating gate on the epitaxial layer through an oxide film, and ion-implant the second conductivity type impurity using the LOCOS oxide film and the insulating gate as a mask. A high-concentration second-conductivity-type drain region and a high-concentration second-conductivity-type source region are formed separately in the well region so as to be exposed at the surface of the polysilicon, and the polysilicon is electrically connected to 0V. A method for manufacturing a semiconductor device, comprising: