JPH10126230A - 信号入力回路 - Google Patents
信号入力回路Info
- Publication number
- JPH10126230A JPH10126230A JP8289131A JP28913196A JPH10126230A JP H10126230 A JPH10126230 A JP H10126230A JP 8289131 A JP8289131 A JP 8289131A JP 28913196 A JP28913196 A JP 28913196A JP H10126230 A JPH10126230 A JP H10126230A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- input
- integration
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0292—Arrangements specific to the receiver end
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Manipulation Of Pulses (AREA)
- Analogue/Digital Conversion (AREA)
- Dc Digital Transmission (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8289131A JPH10126230A (ja) | 1996-10-13 | 1996-10-13 | 信号入力回路 |
US08/948,941 US6037824A (en) | 1996-10-13 | 1997-10-10 | Signal input circuit |
KR1019970052340A KR100291879B1 (ko) | 1996-10-13 | 1997-10-13 | 신호입력회로 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8289131A JPH10126230A (ja) | 1996-10-13 | 1996-10-13 | 信号入力回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10126230A true JPH10126230A (ja) | 1998-05-15 |
Family
ID=17739166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8289131A Pending JPH10126230A (ja) | 1996-10-13 | 1996-10-13 | 信号入力回路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6037824A (ko) |
JP (1) | JPH10126230A (ko) |
KR (1) | KR100291879B1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100713784B1 (ko) * | 1999-07-14 | 2007-05-07 | 후지쯔 가부시끼가이샤 | 수신기, 트랜시버 회로, 신호 전송 방법 및 신호 전송시스템 |
KR20210139481A (ko) | 2019-05-23 | 2021-11-22 | 미쓰비시덴키 가부시키가이샤 | 수신 회로 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6402328B1 (en) * | 1999-01-25 | 2002-06-11 | Gentex Corporation | Automatic dimming mirror using semiconductor light sensor with integral charge collection |
US6278312B1 (en) * | 1999-02-24 | 2001-08-21 | Intel Corporation | Method and apparatus for generating a reference voltage signal derived from complementary signals |
US7124221B1 (en) * | 1999-10-19 | 2006-10-17 | Rambus Inc. | Low latency multi-level communication interface |
US6396329B1 (en) * | 1999-10-19 | 2002-05-28 | Rambus, Inc | Method and apparatus for receiving high speed signals with low latency |
US6756823B1 (en) * | 2000-06-28 | 2004-06-29 | Intel Corporation | Differential sense latch scheme |
US7057672B2 (en) * | 2001-03-29 | 2006-06-06 | Intel Corporation | Method and apparatus for high frequency data transmission and testability in a low voltage, differential swing design |
KR100468749B1 (ko) * | 2002-07-12 | 2005-01-29 | 삼성전자주식회사 | 고속 동작을 위한 플립플롭 |
US8861667B1 (en) | 2002-07-12 | 2014-10-14 | Rambus Inc. | Clock data recovery circuit with equalizer clock calibration |
JP3704112B2 (ja) * | 2002-08-20 | 2005-10-05 | 株式会社東芝 | 信号電圧検出回路 |
US7301373B1 (en) * | 2005-08-04 | 2007-11-27 | Advanced Micro Devices, Inc. | Asymmetric precharged flip flop |
KR100824779B1 (ko) * | 2007-01-11 | 2008-04-24 | 삼성전자주식회사 | 반도체 메모리 장치의 데이터 출력 경로 및 데이터 출력방법 |
US8620523B2 (en) | 2011-06-24 | 2013-12-31 | Gentex Corporation | Rearview assembly with multiple ambient light sensors |
WO2013022731A1 (en) | 2011-08-05 | 2013-02-14 | Gentex Corporation | Optical assembly for a light sensor |
US9207116B2 (en) | 2013-02-12 | 2015-12-08 | Gentex Corporation | Light sensor |
US9870753B2 (en) | 2013-02-12 | 2018-01-16 | Gentex Corporation | Light sensor having partially opaque optic |
CN106461483A (zh) * | 2014-03-27 | 2017-02-22 | 西铁城精密器件株式会社 | 压力检测装置 |
US10008259B1 (en) | 2016-12-07 | 2018-06-26 | Advanced Micro Devices, Inc. | Limiting bitline precharge drive fight current using multiple power domains |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3602826A (en) * | 1969-12-24 | 1971-08-31 | Westinghouse Electric Corp | Adaptive signal detection system |
US3864583A (en) * | 1971-11-11 | 1975-02-04 | Ibm | Detection of digital data using integration techniques |
US4918338A (en) * | 1988-10-04 | 1990-04-17 | North American Philips Corporation | Drain-biassed transresistance device for continuous time filters |
FR2645373A1 (fr) * | 1989-03-28 | 1990-10-05 | Js Telecommunications | Procede et dispositif de reduction du bruit sur un signal codable a plusieurs niveaux predetermines |
US5325065A (en) * | 1992-05-18 | 1994-06-28 | Motorola, Inc. | Detection circuit with dummy integrator to compensate for switch charge insection and amplifier offset voltage |
JP3194314B2 (ja) * | 1993-04-28 | 2001-07-30 | ソニー株式会社 | 同期型回路 |
JPH0863268A (ja) * | 1994-08-23 | 1996-03-08 | Hitachi Ltd | 入出力インタフェース回路装置 |
-
1996
- 1996-10-13 JP JP8289131A patent/JPH10126230A/ja active Pending
-
1997
- 1997-10-10 US US08/948,941 patent/US6037824A/en not_active Expired - Lifetime
- 1997-10-13 KR KR1019970052340A patent/KR100291879B1/ko not_active IP Right Cessation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100713784B1 (ko) * | 1999-07-14 | 2007-05-07 | 후지쯔 가부시끼가이샤 | 수신기, 트랜시버 회로, 신호 전송 방법 및 신호 전송시스템 |
KR20210139481A (ko) | 2019-05-23 | 2021-11-22 | 미쓰비시덴키 가부시키가이샤 | 수신 회로 |
US11418314B2 (en) | 2019-05-23 | 2022-08-16 | Mitsubishi Electric Corporation | Reception circuit |
Also Published As
Publication number | Publication date |
---|---|
KR19980032782A (ko) | 1998-07-25 |
KR100291879B1 (ko) | 2001-06-01 |
US6037824A (en) | 2000-03-14 |
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Legal Events
Date | Code | Title | Description |
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A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040630 |
|
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Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040819 |
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A521 | Written amendment |
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A02 | Decision of refusal |
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