JPH10125099A5 - - Google Patents

Info

Publication number
JPH10125099A5
JPH10125099A5 JP1997276141A JP27614197A JPH10125099A5 JP H10125099 A5 JPH10125099 A5 JP H10125099A5 JP 1997276141 A JP1997276141 A JP 1997276141A JP 27614197 A JP27614197 A JP 27614197A JP H10125099 A5 JPH10125099 A5 JP H10125099A5
Authority
JP
Japan
Prior art keywords
voltage
control gate
memory cells
applying
positive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1997276141A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10125099A (ja
Filing date
Publication date
Application filed filed Critical
Publication of JPH10125099A publication Critical patent/JPH10125099A/ja
Publication of JPH10125099A5 publication Critical patent/JPH10125099A5/ja
Pending legal-status Critical Current

Links

JP27614197A 1996-10-08 1997-10-08 フラッシュｅｅｐｒｏｍの閾値電圧を検査および調整する方法とシステム Pending JPH10125099A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2797196P 1996-10-08 1996-10-08
US027971 1996-10-08

Publications (2)

Publication Number Publication Date
JPH10125099A JPH10125099A (ja) 1998-05-15
JPH10125099A5 true JPH10125099A5 (enExample) 2006-03-02

Family

ID=21840832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27614197A Pending JPH10125099A (ja) 1996-10-08 1997-10-08 フラッシュｅｅｐｒｏｍの閾値電圧を検査および調整する方法とシステム

Country Status (4)

Country Link
US (1) US5909397A (enExample)
EP (1) EP0836196B1 (enExample)
JP (1) JPH10125099A (enExample)
DE (1) DE69735918T2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4229482B2 (ja) * 1997-10-24 2009-02-25 株式会社ルネサステクノロジ フラッシュメモリ内蔵マイクロコンピュータ
KR100305032B1 (ko) * 1999-06-22 2001-11-01 윤종용 반도체 메모리 장치
JP4138173B2 (ja) * 1999-08-26 2008-08-20 株式会社ルネサステクノロジ 不揮発性半導体記憶装置およびその消去方法
US6128219A (en) * 1999-10-27 2000-10-03 Stmicroelectronics, S.R.L. Nonvolatile memory test structure and nonvolatile memory reliability test method
US6684173B2 (en) * 2001-10-09 2004-01-27 Micron Technology, Inc. System and method of testing non-volatile memory cells
US7345918B2 (en) * 2005-08-31 2008-03-18 Micron Technology, Inc. Selective threshold voltage verification and compaction
US7986553B2 (en) * 2007-06-15 2011-07-26 Micron Technology, Inc. Programming of a solid state memory utilizing analog communication of bit patterns
US9711211B2 (en) 2015-10-29 2017-07-18 Sandisk Technologies Llc Dynamic threshold voltage compaction for non-volatile memory

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04222994A (ja) * 1990-12-26 1992-08-12 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US5371706A (en) * 1992-08-20 1994-12-06 Texas Instruments Incorporated Circuit and method for sensing depletion of memory cells
US5428621A (en) * 1992-09-21 1995-06-27 Sundisk Corporation Latent defect handling in EEPROM devices
JPH06251593A (ja) * 1993-02-24 1994-09-09 Matsushita Electron Corp フラッシュメモリの消去あるいは書き込み制御方法
US5424991A (en) * 1993-04-01 1995-06-13 Cypress Semiconductor Corporation Floating gate nonvolatile memory with uniformly erased threshold voltage
US5335198A (en) * 1993-05-06 1994-08-02 Advanced Micro Devices, Inc. Flash EEPROM array with high endurance
US5521867A (en) * 1993-12-01 1996-05-28 Advanced Micro Devices, Inc. Adjustable threshold voltage conversion circuit
US5412603A (en) * 1994-05-06 1995-05-02 Texas Instruments Incorporated Method and circuitry for programming floating-gate memory cell using a single low-voltage supply
EP0757355B1 (en) * 1995-07-31 2000-04-19 STMicroelectronics S.r.l. Mixed parallel-dichotomic serial sensing method for sensing multiple-levels non-volatile memory cells, and sensing circuit actuating such method

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