JPH09212361A5 - - Google Patents

Info

Publication number
JPH09212361A5
JPH09212361A5 JP1996021453A JP2145396A JPH09212361A5 JP H09212361 A5 JPH09212361 A5 JP H09212361A5 JP 1996021453 A JP1996021453 A JP 1996021453A JP 2145396 A JP2145396 A JP 2145396A JP H09212361 A5 JPH09212361 A5 JP H09212361A5
Authority
JP
Japan
Prior art keywords
data
unit
arithmetic
memory
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1996021453A
Other languages
English (en)
Japanese (ja)
Other versions
JP3658072B2 (ja
JPH09212361A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from JP02145396A external-priority patent/JP3658072B2/ja
Priority to JP02145396A priority Critical patent/JP3658072B2/ja
Priority to US08/699,944 priority patent/US5901301A/en
Priority to EP96119559A priority patent/EP0789297B1/en
Priority to DE69627807T priority patent/DE69627807T2/de
Priority to EP02013414A priority patent/EP1265131A3/en
Publication of JPH09212361A publication Critical patent/JPH09212361A/ja
Priority to US09/848,253 priority patent/USRE38679E1/en
Publication of JPH09212361A5 publication Critical patent/JPH09212361A5/ja
Publication of JP3658072B2 publication Critical patent/JP3658072B2/ja
Application granted granted Critical
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

JP02145396A 1996-02-07 1996-02-07 データ処理装置およびデータ処理方法 Expired - Lifetime JP3658072B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP02145396A JP3658072B2 (ja) 1996-02-07 1996-02-07 データ処理装置およびデータ処理方法
US08/699,944 US5901301A (en) 1996-02-07 1996-08-20 Data processor and method of processing data
EP02013414A EP1265131A3 (en) 1996-02-07 1996-12-05 Digital signal processor and method of processing digital signal data
DE69627807T DE69627807T2 (de) 1996-02-07 1996-12-05 Datenprozessor zum gleichzeitigen Dataladen und Durchführung einer multiplizier-addier Operation
EP96119559A EP0789297B1 (en) 1996-02-07 1996-12-05 Data processor loading data and performing multiply-add operation in parallel
US09/848,253 USRE38679E1 (en) 1996-02-07 2001-05-04 Data processor and method of processing data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02145396A JP3658072B2 (ja) 1996-02-07 1996-02-07 データ処理装置およびデータ処理方法

Publications (3)

Publication Number Publication Date
JPH09212361A JPH09212361A (ja) 1997-08-15
JPH09212361A5 true JPH09212361A5 (enExample) 2004-12-09
JP3658072B2 JP3658072B2 (ja) 2005-06-08

Family

ID=12055391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP02145396A Expired - Lifetime JP3658072B2 (ja) 1996-02-07 1996-02-07 データ処理装置およびデータ処理方法

Country Status (4)

Country Link
US (2) US5901301A (enExample)
EP (2) EP0789297B1 (enExample)
JP (1) JP3658072B2 (enExample)
DE (1) DE69627807T2 (enExample)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6219779B1 (en) * 1997-06-16 2001-04-17 Matsushita Electric Industrial Co., Ltd. Constant reconstructing processor which supports reductions in code size
JP3412462B2 (ja) * 1997-07-30 2003-06-03 松下電器産業株式会社 プロセッサ
US6101592A (en) * 1998-12-18 2000-08-08 Billions Of Operations Per Second, Inc. Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
US6324639B1 (en) 1998-03-30 2001-11-27 Matsushita Electric Industrial Co., Ltd. Instruction converting apparatus using parallel execution code
US6212618B1 (en) * 1998-03-31 2001-04-03 Intel Corporation Apparatus and method for performing multi-dimensional computations based on intra-add operation
US6418529B1 (en) * 1998-03-31 2002-07-09 Intel Corporation Apparatus and method for performing intra-add operation
US7395302B2 (en) 1998-03-31 2008-07-01 Intel Corporation Method and apparatus for performing horizontal addition and subtraction
US7392275B2 (en) * 1998-03-31 2008-06-24 Intel Corporation Method and apparatus for performing efficient transformations with horizontal addition and subtraction
US6801995B1 (en) * 1998-08-04 2004-10-05 Agere Systems, Inc. Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes
US7117342B2 (en) * 1998-12-03 2006-10-03 Sun Microsystems, Inc. Implicitly derived register specifiers in a processor
US6615338B1 (en) * 1998-12-03 2003-09-02 Sun Microsystems, Inc. Clustered architecture in a VLIW processor
US7114056B2 (en) 1998-12-03 2006-09-26 Sun Microsystems, Inc. Local and global register partitioning in a VLIW processor
JP3842474B2 (ja) 1999-02-02 2006-11-08 株式会社ルネサステクノロジ データ処理装置
US6504495B1 (en) * 1999-02-17 2003-01-07 Arm Limited Clipping data values in a data processing system
DE50014621D1 (de) * 1999-05-06 2007-10-18 Siemens Ag Kommunikationseinrichtung mit Mitteln zur Echtzeitverarbeitung von zu übertragenden Nutzdaten
US7107302B1 (en) 1999-05-12 2006-09-12 Analog Devices, Inc. Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units
EP1188112A2 (en) * 1999-05-12 2002-03-20 Analog Devices, Inc. Digital signal processor computation core
US7111155B1 (en) 1999-05-12 2006-09-19 Analog Devices, Inc. Digital signal processor computation core with input operand selection from operand bus for dual operations
US6859872B1 (en) 1999-05-12 2005-02-22 Analog Devices, Inc. Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation
US6820189B1 (en) * 1999-05-12 2004-11-16 Analog Devices, Inc. Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation
JP2001022689A (ja) * 1999-07-06 2001-01-26 Mitsubishi Electric Corp 出力ｆｉｆｏデータ転送制御装置
US6557096B1 (en) 1999-10-25 2003-04-29 Intel Corporation Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types
US6832306B1 (en) 1999-10-25 2004-12-14 Intel Corporation Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions
US6446195B1 (en) * 2000-01-31 2002-09-03 Intel Corporation Dyadic operations instruction processor with configurable functional blocks
US6408376B1 (en) 1999-10-25 2002-06-18 Intel Corporation Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously
US6330660B1 (en) * 1999-10-25 2001-12-11 Vxtel, Inc. Method and apparatus for saturated multiplication and accumulation in an application specific signal processor
WO2001052183A1 (en) * 2000-01-07 2001-07-19 Intensys Corporation Method and apparatus to transform specification of functions for processing grid-structured data
US6732203B2 (en) * 2000-01-31 2004-05-04 Intel Corporation Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus
US6959222B1 (en) * 2000-04-13 2005-10-25 New Japan Radio Co., Ltd. Accelerator engine for processing functions used in audio algorithms
JP3845814B2 (ja) * 2000-08-10 2006-11-15 株式会社テルミナス・テクノロジー 連想メモリとその検索方法及びルータとネットワークシステム
JP2002073330A (ja) 2000-08-28 2002-03-12 Mitsubishi Electric Corp データ処理装置
US7003093B2 (en) * 2000-09-08 2006-02-21 Intel Corporation Tone detection for integrated telecommunications processing
US20020116186A1 (en) * 2000-09-09 2002-08-22 Adam Strauss Voice activity detector for integrated telecommunications processing
JP2002229779A (ja) 2001-02-02 2002-08-16 Mitsubishi Electric Corp 情報処理装置
JP4502532B2 (ja) * 2001-02-23 2010-07-14 株式会社ルネサステクノロジ データ処理装置
US20030219113A1 (en) * 2002-05-21 2003-11-27 Bershad Neil J. Echo canceller with double-talk and channel impulse response adaptation
US7380151B1 (en) 2002-12-11 2008-05-27 National Semiconductor Corporation Apparatus and method for asynchronously clocking the processing of a wireless communication signal by multiple processors
US7016695B1 (en) 2002-12-11 2006-03-21 National Semiconductor Corporation Apparatus and method for processing a deterministic data flow associated with a wireless communication signal
US7366352B2 (en) * 2003-03-20 2008-04-29 International Business Machines Corporation Method and apparatus for performing fast closest match in pattern recognition
CN100595731C (zh) * 2003-03-21 2010-03-24 凌阳科技股份有限公司 利用同位检查以进行指令模式切换的处理器及方法
US7194601B2 (en) * 2003-04-03 2007-03-20 Via-Cyrix, Inc Low-power decode circuitry and method for a processor having multiple decoders
US7680990B2 (en) * 2003-05-30 2010-03-16 Hewlett-Packard Development Company, L.P. Superword memory-access instructions for data processor
US7017127B1 (en) 2003-06-02 2006-03-21 National Semiconductor Corporation Method and system for enabling energy efficient wireless connectivity
US7793072B2 (en) * 2003-10-31 2010-09-07 International Business Machines Corporation Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands
US9047094B2 (en) * 2004-03-31 2015-06-02 Icera Inc. Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor
US7949856B2 (en) 2004-03-31 2011-05-24 Icera Inc. Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit
US8484441B2 (en) * 2004-03-31 2013-07-09 Icera Inc. Apparatus and method for separate asymmetric control processing and data path processing in a configurable dual path processor that supports instructions having different bit widths
US7437536B2 (en) * 2004-05-03 2008-10-14 Sony Computer Entertainment Inc. Systems and methods for task migration
JP2006004042A (ja) * 2004-06-16 2006-01-05 Renesas Technology Corp データ処理装置
US6980148B1 (en) 2004-12-07 2005-12-27 National Semiconductor Corporation Pipelined analog to digital converter that is configurable based on wireless communication protocol
US7205923B1 (en) 2004-12-07 2007-04-17 National Semiconductor Corporation Pipelined analog to digital converter that is configurable based on mode and strength of received signal
GB2421092B (en) * 2004-12-07 2008-12-03 Hewlett Packard Development Co Bufferless writing of data to memory
US7193553B1 (en) 2004-12-07 2007-03-20 National Semiconductor Corporation Analog to digital converter with power-saving adjustable resolution
US7370136B2 (en) * 2005-01-26 2008-05-06 Stmicroelectronics, Inc. Efficient and flexible sequencing of data processing units extending VLIW architecture
US7581082B2 (en) * 2005-05-13 2009-08-25 Texas Instruments Incorporated Software source transfer selects instruction word sizes
US7912887B2 (en) * 2006-05-10 2011-03-22 Qualcomm Incorporated Mode-based multiply-add recoding for denormal operands
GB2464292A (en) * 2008-10-08 2010-04-14 Advanced Risc Mach Ltd SIMD processor circuit for performing iterative SIMD multiply-accumulate operations
US8161090B2 (en) * 2008-12-05 2012-04-17 Crossfield Technology LLC Floating-point fused add-subtract unit
EP2473918B1 (en) * 2009-09-04 2019-05-08 Intel Corporation Method for generating a set of instruction compaction schemes, method for compacting a program according to the generated set, and programmable processor capable of executing a program thus compacted
JP6050721B2 (ja) * 2012-05-25 2016-12-21 株式会社半導体エネルギー研究所 半導体装置
CN105378651B (zh) * 2013-05-24 2018-09-18 相干逻辑公司 具有可编程优化的存储器-网络处理器
JP6378515B2 (ja) * 2014-03-26 2018-08-22 株式会社メガチップス Ｖｌｉｗプロセッサ
JP2017228213A (ja) * 2016-06-24 2017-12-28 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US11417373B2 (en) 2020-12-09 2022-08-16 Micron Technology, Inc. Neuromorphic computing devices and methods
JP7782247B2 (ja) * 2021-12-15 2025-12-09 富士通株式会社 演算処理装置および演算処理方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5344130A (en) * 1976-10-05 1978-04-20 Toshiba Corp Floating access memory device
JPS57113144A (en) * 1980-12-30 1982-07-14 Seiko Epson Corp Stored program computer
JPS60134938A (ja) * 1983-12-23 1985-07-18 Nec Corp レジスタフアイル読出し方式
JPS60138640A (ja) * 1983-12-27 1985-07-23 Nec Corp レジスタフアイル書込み方式
US4819152A (en) * 1985-04-05 1989-04-04 Raytheon Company Method and apparatus for addressing a memory by array transformations
JPH0719246B2 (ja) * 1988-01-11 1995-03-06 三洋電機株式会社 デジタル信号処理装置
US5201039A (en) * 1987-09-30 1993-04-06 Mitsubishi Denki Kabushiki Kaisha Multiple address-space data processor with addressable register and context switching
US4862407A (en) * 1987-10-05 1989-08-29 Motorola, Inc. Digital signal processing apparatus
US5134711A (en) * 1988-05-13 1992-07-28 At&T Bell Laboratories Computer with intelligent memory system
NL8902040A (nl) * 1988-08-19 1990-03-16 Tektronix Inc Met hoge snelheid werkende directe geheugentoegangsbesturing voor test- en meetinstrumenten.
JPH02103632A (ja) * 1988-10-12 1990-04-16 Nec Corp 演算処理装置
JP2816248B2 (ja) * 1989-11-08 1998-10-27 株式会社日立製作所 データプロセッサ
JPH03186928A (ja) * 1989-12-16 1991-08-14 Mitsubishi Electric Corp データ処理装置
US5299321A (en) * 1990-12-18 1994-03-29 Oki Electric Industry Co., Ltd. Parallel processing device to operate with parallel execute instructions
KR950015181B1 (ko) * 1991-07-01 1995-12-23 후지쓰 가부시끼가이샤 곱셈-합 연산장치
JPH05233281A (ja) * 1992-02-21 1993-09-10 Toshiba Corp 電子計算機
US5485629A (en) * 1993-01-22 1996-01-16 Intel Corporation Method and apparatus for executing control flow instructions in a control flow pipeline in parallel with arithmetic instructions being executed in arithmetic pipelines
US5825921A (en) * 1993-03-19 1998-10-20 Intel Corporation Memory transfer apparatus and method useful within a pattern recognition system
JPH07114469A (ja) * 1993-10-18 1995-05-02 Mitsubishi Electric Corp データ処理装置
EP0651321B1 (en) * 1993-10-29 2001-11-14 Advanced Micro Devices, Inc. Superscalar microprocessors
JPH07176380A (ja) 1993-12-21 1995-07-14 Casio Comput Co Ltd エレクトロルミネッセンス素子
US5630083A (en) * 1994-03-01 1997-05-13 Intel Corporation Decoder for decoding multiple instructions in parallel
US5812810A (en) * 1994-07-01 1998-09-22 Digital Equipment Corporation Instruction coding to support parallel execution of programs
JP2931890B2 (ja) 1995-07-12 1999-08-09 三菱電機株式会社 データ処理装置

Similar Documents

Publication Publication Date Title
JPH09212361A5 (enExample)
EP0789297B1 (en) Data processor loading data and performing multiply-add operation in parallel
US3646522A (en) General purpose optimized microprogrammed miniprocessor
JP3856737B2 (ja) データ処理装置
JPH11154114A (ja) 複数データ・フェッチのアーキテクチャを使ってテーブル・ルックアップを実行するためのシステムおよび方法
JPH1091443A (ja) 情報処理回路、マイクロコンピュータ及び電子機器
JP3670668B2 (ja) データ処理装置
EP0855648A2 (en) Data processing with parallel or sequential execution of program instructions
EP3340037B1 (en) A data processing apparatus and method for controlling vector memory accesses
JP3789583B2 (ja) データ処理装置
US5757685A (en) Data processing system capable of processing long word data
US11714641B2 (en) Vector generating instruction for generating a vector comprising a sequence of elements that wraps as required
JP3866513B2 (ja) データストリーミングのためのコンピュータのプロセッサ及び方法
US6078940A (en) Microprocessor with an instruction for multiply and left shift with saturate
US5958000A (en) Two-bit booth multiplier with reduced data path width
JP2004086837A (ja) データ処理装置
JP4073721B2 (ja) データ処理装置
US6055628A (en) Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks
JP2002544587A (ja) デジタル信号プロセッサ計算コア
JP4502532B2 (ja) データ処理装置
JP2002229779A (ja) 情報処理装置
Lempel et al. Intel's MMX/sup TM/technology-a new instruction set extension
JP2001504956A (ja) データ処理システム・レジスタ制御
US5446909A (en) Binary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operand
US6115805A (en) Non-aligned double word fetch buffer