DE69627807T2 - Datenprozessor zum gleichzeitigen Dataladen und Durchführung einer multiplizier-addier Operation - Google Patents
Datenprozessor zum gleichzeitigen Dataladen und Durchführung einer multiplizier-addier Operation Download PDFInfo
- Publication number
- DE69627807T2 DE69627807T2 DE69627807T DE69627807T DE69627807T2 DE 69627807 T2 DE69627807 T2 DE 69627807T2 DE 69627807 T DE69627807 T DE 69627807T DE 69627807 T DE69627807 T DE 69627807T DE 69627807 T2 DE69627807 T2 DE 69627807T2
- Authority
- DE
- Germany
- Prior art keywords
- data
- register
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- unit
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
- G06F9/30014—Arithmetic instructions with variable precision
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/355—Indexed addressing
- G06F9/3552—Indexed addressing using wraparound, e.g. modulo or circular addressing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/3822—Parallel decoding, e.g. parallel decode units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2145396 | 1996-02-07 | ||
| JP02145396A JP3658072B2 (ja) | 1996-02-07 | 1996-02-07 | データ処理装置およびデータ処理方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69627807D1 DE69627807D1 (de) | 2003-06-05 |
| DE69627807T2 true DE69627807T2 (de) | 2004-03-11 |
Family
ID=12055391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69627807T Expired - Lifetime DE69627807T2 (de) | 1996-02-07 | 1996-12-05 | Datenprozessor zum gleichzeitigen Dataladen und Durchführung einer multiplizier-addier Operation |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US5901301A (enExample) |
| EP (2) | EP1265131A3 (enExample) |
| JP (1) | JP3658072B2 (enExample) |
| DE (1) | DE69627807T2 (enExample) |
Families Citing this family (65)
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| US6219779B1 (en) * | 1997-06-16 | 2001-04-17 | Matsushita Electric Industrial Co., Ltd. | Constant reconstructing processor which supports reductions in code size |
| JP3412462B2 (ja) * | 1997-07-30 | 2003-06-03 | 松下電器産業株式会社 | プロセッサ |
| US6101592A (en) * | 1998-12-18 | 2000-08-08 | Billions Of Operations Per Second, Inc. | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions |
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| US6418529B1 (en) | 1998-03-31 | 2002-07-09 | Intel Corporation | Apparatus and method for performing intra-add operation |
| US7392275B2 (en) * | 1998-03-31 | 2008-06-24 | Intel Corporation | Method and apparatus for performing efficient transformations with horizontal addition and subtraction |
| US7395302B2 (en) | 1998-03-31 | 2008-07-01 | Intel Corporation | Method and apparatus for performing horizontal addition and subtraction |
| US6212618B1 (en) * | 1998-03-31 | 2001-04-03 | Intel Corporation | Apparatus and method for performing multi-dimensional computations based on intra-add operation |
| US6801995B1 (en) * | 1998-08-04 | 2004-10-05 | Agere Systems, Inc. | Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes |
| US7117342B2 (en) * | 1998-12-03 | 2006-10-03 | Sun Microsystems, Inc. | Implicitly derived register specifiers in a processor |
| US7114056B2 (en) | 1998-12-03 | 2006-09-26 | Sun Microsystems, Inc. | Local and global register partitioning in a VLIW processor |
| US6615338B1 (en) * | 1998-12-03 | 2003-09-02 | Sun Microsystems, Inc. | Clustered architecture in a VLIW processor |
| JP3842474B2 (ja) | 1999-02-02 | 2006-11-08 | 株式会社ルネサステクノロジ | データ処理装置 |
| US6504495B1 (en) * | 1999-02-17 | 2003-01-07 | Arm Limited | Clipping data values in a data processing system |
| DE50014621D1 (de) * | 1999-05-06 | 2007-10-18 | Siemens Ag | Kommunikationseinrichtung mit Mitteln zur Echtzeitverarbeitung von zu übertragenden Nutzdaten |
| EP2267896A3 (en) * | 1999-05-12 | 2013-02-20 | Analog Devices, Inc. | Method for implementing finite impulse response filters |
| US6820189B1 (en) * | 1999-05-12 | 2004-11-16 | Analog Devices, Inc. | Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation |
| US6859872B1 (en) | 1999-05-12 | 2005-02-22 | Analog Devices, Inc. | Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation |
| US7111155B1 (en) | 1999-05-12 | 2006-09-19 | Analog Devices, Inc. | Digital signal processor computation core with input operand selection from operand bus for dual operations |
| US7107302B1 (en) | 1999-05-12 | 2006-09-12 | Analog Devices, Inc. | Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units |
| JP2001022689A (ja) * | 1999-07-06 | 2001-01-26 | Mitsubishi Electric Corp | 出力fifoデータ転送制御装置 |
| US6446195B1 (en) * | 2000-01-31 | 2002-09-03 | Intel Corporation | Dyadic operations instruction processor with configurable functional blocks |
| US6832306B1 (en) | 1999-10-25 | 2004-12-14 | Intel Corporation | Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions |
| US6408376B1 (en) | 1999-10-25 | 2002-06-18 | Intel Corporation | Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously |
| US6557096B1 (en) | 1999-10-25 | 2003-04-29 | Intel Corporation | Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types |
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| US6959222B1 (en) * | 2000-04-13 | 2005-10-25 | New Japan Radio Co., Ltd. | Accelerator engine for processing functions used in audio algorithms |
| JP3845814B2 (ja) * | 2000-08-10 | 2006-11-15 | 株式会社テルミナス・テクノロジー | 連想メモリとその検索方法及びルータとネットワークシステム |
| JP2002073330A (ja) * | 2000-08-28 | 2002-03-12 | Mitsubishi Electric Corp | データ処理装置 |
| US7003093B2 (en) * | 2000-09-08 | 2006-02-21 | Intel Corporation | Tone detection for integrated telecommunications processing |
| US20020116186A1 (en) * | 2000-09-09 | 2002-08-22 | Adam Strauss | Voice activity detector for integrated telecommunications processing |
| JP2002229779A (ja) | 2001-02-02 | 2002-08-16 | Mitsubishi Electric Corp | 情報処理装置 |
| JP4502532B2 (ja) * | 2001-02-23 | 2010-07-14 | 株式会社ルネサステクノロジ | データ処理装置 |
| US20030219113A1 (en) * | 2002-05-21 | 2003-11-27 | Bershad Neil J. | Echo canceller with double-talk and channel impulse response adaptation |
| US7380151B1 (en) | 2002-12-11 | 2008-05-27 | National Semiconductor Corporation | Apparatus and method for asynchronously clocking the processing of a wireless communication signal by multiple processors |
| US7016695B1 (en) | 2002-12-11 | 2006-03-21 | National Semiconductor Corporation | Apparatus and method for processing a deterministic data flow associated with a wireless communication signal |
| US7366352B2 (en) * | 2003-03-20 | 2008-04-29 | International Business Machines Corporation | Method and apparatus for performing fast closest match in pattern recognition |
| CN100595731C (zh) * | 2003-03-21 | 2010-03-24 | 凌阳科技股份有限公司 | 利用同位检查以进行指令模式切换的处理器及方法 |
| US7194601B2 (en) * | 2003-04-03 | 2007-03-20 | Via-Cyrix, Inc | Low-power decode circuitry and method for a processor having multiple decoders |
| US7680990B2 (en) * | 2003-05-30 | 2010-03-16 | Hewlett-Packard Development Company, L.P. | Superword memory-access instructions for data processor |
| US7017127B1 (en) | 2003-06-02 | 2006-03-21 | National Semiconductor Corporation | Method and system for enabling energy efficient wireless connectivity |
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| US7949856B2 (en) * | 2004-03-31 | 2011-05-24 | Icera Inc. | Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit |
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| JP2006004042A (ja) * | 2004-06-16 | 2006-01-05 | Renesas Technology Corp | データ処理装置 |
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| US6980148B1 (en) | 2004-12-07 | 2005-12-27 | National Semiconductor Corporation | Pipelined analog to digital converter that is configurable based on wireless communication protocol |
| US7193553B1 (en) | 2004-12-07 | 2007-03-20 | National Semiconductor Corporation | Analog to digital converter with power-saving adjustable resolution |
| US7205923B1 (en) | 2004-12-07 | 2007-04-17 | National Semiconductor Corporation | Pipelined analog to digital converter that is configurable based on mode and strength of received signal |
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| US7581082B2 (en) * | 2005-05-13 | 2009-08-25 | Texas Instruments Incorporated | Software source transfer selects instruction word sizes |
| US7912887B2 (en) * | 2006-05-10 | 2011-03-22 | Qualcomm Incorporated | Mode-based multiply-add recoding for denormal operands |
| GB2464292A (en) * | 2008-10-08 | 2010-04-14 | Advanced Risc Mach Ltd | SIMD processor circuit for performing iterative SIMD multiply-accumulate operations |
| US8161090B2 (en) * | 2008-12-05 | 2012-04-17 | Crossfield Technology LLC | Floating-point fused add-subtract unit |
| KR101401244B1 (ko) * | 2009-09-04 | 2014-05-28 | 실리콘 하이브 비.브이. | 방법 및 장치 및 기록 매체 |
| JP6050721B2 (ja) * | 2012-05-25 | 2016-12-21 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| WO2014190263A2 (en) * | 2013-05-24 | 2014-11-27 | Coherent Logix, Incorporated | Memory-network processor with programmable optimizations |
| JP6378515B2 (ja) * | 2014-03-26 | 2018-08-22 | 株式会社メガチップス | Vliwプロセッサ |
| JP2017228213A (ja) * | 2016-06-24 | 2017-12-28 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
| US11417373B2 (en) * | 2020-12-09 | 2022-08-16 | Micron Technology, Inc. | Neuromorphic computing devices and methods |
| JP7782247B2 (ja) * | 2021-12-15 | 2025-12-09 | 富士通株式会社 | 演算処理装置および演算処理方法 |
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-
1996
- 1996-02-07 JP JP02145396A patent/JP3658072B2/ja not_active Expired - Lifetime
- 1996-08-20 US US08/699,944 patent/US5901301A/en not_active Ceased
- 1996-12-05 EP EP02013414A patent/EP1265131A3/en not_active Withdrawn
- 1996-12-05 EP EP96119559A patent/EP0789297B1/en not_active Expired - Lifetime
- 1996-12-05 DE DE69627807T patent/DE69627807T2/de not_active Expired - Lifetime
-
2001
- 2001-05-04 US US09/848,253 patent/USRE38679E1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1265131A2 (en) | 2002-12-11 |
| EP1265131A3 (en) | 2007-05-30 |
| JPH09212361A (ja) | 1997-08-15 |
| EP0789297B1 (en) | 2003-05-02 |
| EP0789297A2 (en) | 1997-08-13 |
| DE69627807D1 (de) | 2003-06-05 |
| JP3658072B2 (ja) | 2005-06-08 |
| USRE38679E1 (en) | 2004-12-28 |
| EP0789297A3 (en) | 1998-12-02 |
| US5901301A (en) | 1999-05-04 |
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|---|---|---|---|
| 8364 | No opposition during term of opposition |