JPH0834225B2 - 超高密度パッドアレイ・チップキャリアを接地する方法 - Google Patents

超高密度パッドアレイ・チップキャリアを接地する方法

Info

Publication number
JPH0834225B2
JPH0834225B2 JP2507470A JP50747090A JPH0834225B2 JP H0834225 B2 JPH0834225 B2 JP H0834225B2 JP 2507470 A JP2507470 A JP 2507470A JP 50747090 A JP50747090 A JP 50747090A JP H0834225 B2 JPH0834225 B2 JP H0834225B2
Authority
JP
Japan
Prior art keywords
die pad
die
chip carrier
runner
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2507470A
Other languages
English (en)
Other versions
JPH04505235A (ja
Inventor
ジェイ フリーマン・ブルース
エム マイルス・バリー
ジェイ ジャスキー・フランク
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPH04505235A publication Critical patent/JPH04505235A/ja
Publication of JPH0834225B2 publication Critical patent/JPH0834225B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 技術分野 この発明は一般的には超高密度パッドアレイ・チップ
キャリアを製造する方法に関し、より特定的には超高密
度パッドアレイ・チップキャリアにおける集積回路（I
C）装置を接地するための方法に関する。
背景技術 超高密度チップキャリア・アセンブリの接地（ground
ing）は通常基板上のグランドとして作用する導電性ラ
ンナから金属化ポリイミドフィルムのダイパッドにワイ
ヤボンドする必要がある。チップキャリア・アセンブリ
におけるワイヤボンディングはワイヤをボンディングす
るのに必要なより大きなダイパッドの大きさ、より大き
な製造および金属コスト、そして金のボンディングワイ
ヤのような典型的なボンディングワイヤの低い電流伝達
能力のため都合が悪い。
金属化ポリイミドフィルムへのワイヤボンディングを
除去することはいくつかの望ましくない影響を低減す
る。第１に、ワイヤボンディングはワイヤボンダがワイ
ヤを金属化ポリイミドフィルムのダイパッドの上のダイ
に近接して位置付けることを許容するためにより大きな
ダイパッドを必要とする。さらに、（金属化アルミナに
対し）ポリイミドフィルムはその柔順な性質のため貧弱
なワイヤボンドを生成する。さらに、ワイヤボンドを除
去することはポリイミドのダイパッド上の金属層を除去
することを許容するが、それはダイパッドへのワイヤボ
ンディングが必要なくなるからである。ワイヤボンディ
ングはオペレータが、信頼性あるボンディングを行うた
めにセラミックのチップキャリアの形状からポリイミド
フィルムの形状へのような、ワイヤボンダのパラメータ
を変更することを要求する。高電力の集積回路装置をポ
リイミドフィルムのダイパッドから導電性ランナに対し
ワイヤボンドを用いて接地することは典型的なボンディ
ングワイヤの不十分な電流伝達能力のため効率の悪い半
導体接地方法である。本発明による接地されたワイヤボ
ンドの廃棄は、チップキャリア・アセンブリの効率およ
び有効性を増大しながら、製造コストおよび製造時間を
低減する。
発明の概要 従って、本発明の目的は、半導体ダイの背面または底
部をチップキャリアのベースに接地するための方法を提
供し上に述べた欠点を克服することにある。
要約すれば、本発明によれば、適切な誘電材料により
形成されたダイパッドはその中に形成された穴を有し、
それによりその頭部および底部面の間に貫通路を提供す
る。このダイパッドはチップキャリアのベースに固定さ
れる。前記貫通路は導電性材料によりダイの底部面の導
電性ランナへの相互接続を許容する。
図面の簡単な説明 第１図は、導電性領域の典型的なパターンを有するチ
ップキャリアの頭部平面図である。
第２図は、本発明に関わるチップキャリア、ダイパッ
ド、および半導体ダイの断面図を示す。
第３図は、本発明に関わるチップキャリアのベースの
頭部に置かれたダイパッドを備えたチップキャリアベー
スを示す頭部平面図である。
好ましい実施例の詳細な説明 第１図を参照すると、その上に配置された導電性領域
（または金属ランナ）（104）を有するアルミナセラミ
ック基板100が示されている。これらの導電性領域のい
くつかは共通グランドポイントとして作用する金属製ラ
ンド（200）において終端する。好ましくは、該金属製
ランドは、もちろん他の形状も使用できるが、基板の設
計に依存する大きさを有する四角形となっている。本発
明によれば0.020インチ×0.020インチ（0.051センチメ
ートル×0.051センチメートル）の都合のよい大きさが
アセンブリにとって好適である。金属性ランド200は第
２図に示されるダイパッド（108）におけるスルーホー
ルのすぐ下に配置されている。
第２図を参照すると、ダイパッド（108）が効率的な
量の接着剤、好ましくはデュポン社によって製造された
Pyraluxアクリル性接着剤（106）により導電性領域（10
4）の少なくとも一部に固定されている。金属化された
（metalized）あるいは金属化されていない、ダイパッ
ド（108）は0.002インチ（0.005センチメートル）の厚
さのポリイミドフィルムおよび0.001インチ（0.003セン
チメートル）のデュポン社のPyralux改良型アクリル性
接着剤（106）によって積層されたものからなる。ダイ
パッドが基板上に取付けられる前に（好ましくは、直径
0.020インチ（0.051センチメートル）から0.100インチ
（0.255センチメートル）の）穴がポリイミドフィルム
のダイパッドおよび付着されたPyraluxアクリル性接着
剤に形成される。この穴はセラミック基板（100）上の
接地された金属製ランド（200）の上に装着するように
ダイパッド（106）に配置される。最適には、スルーホ
ール（102）に充填された半田は技術上よく知られてい
るように基板（104）の導電性領域に電子的に接続され
る。
第２図および第３図を参照すると、ダイパッドおよび
アクリル性接着剤が次に基板上に置かれ、これは次に積
層される。積層プロセスはダイパッド（108）、アクリ
ル性接着剤（106）および導電性領域（104）の間の緊密
な接合を生じさせる。
好ましくは、銀充填エポキシからなる導電性材料（11
0）はダイパッド（108）およびアクリル性接着剤（10
6）に形成されたスルーホールを通って流れ基板（100）
上の接地された金属製ランド（200）と接触する。銀充
填エポキシはまたダイパッドの頭部面上に付加され、ダ
イ（112）が組立てプロセスにおいてエポキシ中に置か
れた時ダイ（112）の底部面と接地された金属製ランド
（200）との間に電子的接続を生成する。
最後にワイヤボンド（114）は基板上の種々の導電性
領域（104）から半導体ダイ（112）に接続できる。
───────────────────────────────────────────────────── フロントページの続き (72)発明者 ジャスキー・フランク ジェイ アメリカ合衆国フロリダ州 33065、コー ラル・スプリングス、ノース・ウエスト・ シックスティナインス・テラス 4103 (56)参考文献 特開 昭59−200427（ＪＰ，Ａ) 特開 昭59−207645（ＪＰ，Ａ)

Claims (5)

    【特許請求の範囲】
  1. 【請求項１】半導体チップを装着するためのチップキャ
    リア・アセンブリであって、 半導体ダイ、 金属ランナを含むアルミナセラミックのチップキャリア
    ベース、 前記チップキャリアベース上に設けられかつ前記半導体
    ダイと前記キャリアベースとの間に配置された少なくと
    も１つの通路を有する非導電性ダイパッド、 前記半導体ダイおよび少なくとも１つの前記金属ランナ
    を前記ダイパッドの前記通路を介して相互接続する導電
    性材料、 を具備する半導体チップを装着するためのチップキャリ
    ア・アセンブリ。
  2. 【請求項２】前記導電性材料は銀充填エポキシからな
    る、請求の範囲第１項に記載のチップキャリア・アセン
    ブリ。
  3. 【請求項３】前記通路は前記金属ランナの真上に配置さ
    れた前記ダイパッドを通る打抜き穴からなる、請求の範
    囲第１項に記載のチップキャリア・アセンブリ。
  4. 【請求項４】チップキャリア・アセンブリを組立てる方
    法であって、 （ａ）セラミックベースを準備する段階、 （ｂ）ダイパッドにアクリル性接着剤を該接着剤が前記
    ダイパッドに付着するが硬化を始めないような温度で積
    層しかつ前記ダイパッドおよび付着されたアクリル性接
    着剤を通る穴を打抜く段階、 （ｃ）前記ダイパッドをあらかじめ加熱したセラミック
    ベース上に取付け、ダイパッドの前記打抜き穴を接地さ
    れた導電性ランナの真上に位置付け、ダイパッド接合ア
    センブリを形成する段階、 （ｄ）前記ダイパッド接合アセンブリを前記アクリル性
    接着剤が完全に硬化するよう加熱積層する段階、 （ｅ）銀充填エポキシを前記ダイパッドの中間に与え、
    前記銀充填エポキシを、該エポキシ内に置かれた、ダイ
    と前記導電性ランナとの間に電子的接続を形成するよう
    にダイの前記通路に押し通す段階、 （ｆ）前記ダイを銀充填エポキシ上に載置し、それによ
    りダイの背面と導電性ランナとの間の電子的接続を形成
    する段階、 を具備するチップキャリア・アセンブリを組立てる方
    法。
  5. 【請求項５】半導体をチップキャリア・アセンブリを介
    して接地する方法であって、 （ａ）金属化領域を有する基板を提供する段階、 （ｂ）接着剤をポリイミドフィルムのダイパッドに該接
    着剤を硬化することなく前記ダイパッドに接着させる温
    度で付加する段階、 （ｃ）ダイパッドおよび硬化していないアクリル性接着
    剤の双方を通る穴を打抜く段階であって、前記穴は前記
    基板上の金属化領域上に配置されるような位置に設けら
    れるもの、 （ｄ）前記ダイパッドを基板上に取付け、ダイパッドの
    前記打抜かれた穴を接地された導電性ランナの真上に位
    置付け、ダイパッド接合アセンブリを形成する段階、 （ｅ）前記ダイパッド接合アセンブリを加熱積層して前
    記アクリル性接着剤を完全に硬化させる段階、 （ｆ）銀充填エポキシを前記ダイパッドの中央に与え、
    該銀充填エポキシを、該エポキシ内に配置された、ダイ
    と前記導電性ランナとの間に電子的接続を形成するよう
    に前記銀充填エポキシをダイパッドの前記打抜かれた穴
    に通させる段階、 を具備する半導体をチップキャリア・アセンブリを介し
    て接地する方法。
JP2507470A 1989-05-01 1990-04-09 超高密度パッドアレイ・チップキャリアを接地する方法 Expired - Lifetime JPH0834225B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/345,280 US5077633A (en) 1989-05-01 1989-05-01 Grounding an ultra high density pad array chip carrier
US345,280 1989-05-01
PCT/US1990/001828 WO1990013991A1 (en) 1989-05-01 1990-04-09 Method of grounding an ultra high density pad array chip carrier

Publications (2)

Publication Number Publication Date
JPH04505235A JPH04505235A (ja) 1992-09-10
JPH0834225B2 true JPH0834225B2 (ja) 1996-03-29

Family

ID=23354353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2507470A Expired - Lifetime JPH0834225B2 (ja) 1989-05-01 1990-04-09 超高密度パッドアレイ・チップキャリアを接地する方法

Country Status (6)

Country Link
US (1) US5077633A (ja)
EP (1) EP0471003B1 (ja)
JP (1) JPH0834225B2 (ja)
AT (1) ATE114213T1 (ja)
DE (1) DE69014202T2 (ja)
WO (1) WO1990013991A1 (ja)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5175612A (en) * 1989-12-19 1992-12-29 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
KR970011619B1 (ko) * 1990-12-21 1997-07-12 모토로라 인코포레이티드 리드레스 패드 배열 칩 캐리어 패키지 및 그 제조방법
DE69229661T2 (de) * 1991-04-26 1999-12-30 Citizen Watch Co Ltd Verfahren zur Herstellung einer Anschlusstruktur für eine Halbleiteranordnung
US5249098A (en) * 1991-08-22 1993-09-28 Lsi Logic Corporation Semiconductor device package with solder bump electrical connections on an external surface of the package
JPH05109922A (ja) * 1991-10-21 1993-04-30 Nec Corp 半導体装置
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5517752A (en) * 1992-05-13 1996-05-21 Fujitsu Limited Method of connecting a pressure-connector terminal of a device with a terminal electrode of a substrate
US5592025A (en) * 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
US5479319A (en) * 1992-12-30 1995-12-26 Interconnect Systems, Inc. Multi-level assemblies for interconnecting integrated circuits
US5481436A (en) * 1992-12-30 1996-01-02 Interconnect Systems, Inc. Multi-level assemblies and methods for interconnecting integrated circuits
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
US5820014A (en) 1993-11-16 1998-10-13 Form Factor, Inc. Solder preforms
KR100437437B1 (ko) 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 반도체 패키지의 제조법 및 반도체 패키지
US5745985A (en) * 1995-06-23 1998-05-05 Texas Instruments Incorporated Method of attaching a semiconductor microchip to a circuit board
US6097099A (en) * 1995-10-20 2000-08-01 Texas Instruments Incorporated Electro-thermal nested die-attach design
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US8033838B2 (en) 1996-02-21 2011-10-11 Formfactor, Inc. Microelectronic contact structure
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
JP3928753B2 (ja) * 1996-08-06 2007-06-13 日立化成工業株式会社 マルチチップ実装法、および接着剤付チップの製造方法
US6051888A (en) * 1997-04-07 2000-04-18 Texas Instruments Incorporated Semiconductor package and method for increased thermal dissipation of flip-chip semiconductor package
FR2790905A1 (fr) * 1999-03-09 2000-09-15 Sagem Composant electrique de puissance a montage par brasage sur un support et procede de montage correspondant
GB2356737A (en) * 1999-11-26 2001-05-30 Nokia Mobile Phones Ltd Ground Plane for a Semiconductor Chip
KR101139181B1 (ko) * 2004-01-30 2012-04-26 미쓰비시 가가꾸 가부시키가이샤 Ｌｅｄ 및 ｌｅｄ의 장착 구조
US8629539B2 (en) * 2012-01-16 2014-01-14 Allegro Microsystems, Llc Methods and apparatus for magnetic sensor having non-conductive die paddle
US10234513B2 (en) 2012-03-20 2019-03-19 Allegro Microsystems, Llc Magnetic field sensor integrated circuit with integral ferromagnetic material
US9812588B2 (en) 2012-03-20 2017-11-07 Allegro Microsystems, Llc Magnetic field sensor integrated circuit with integral ferromagnetic material
US10991644B2 (en) 2019-08-22 2021-04-27 Allegro Microsystems, Llc Integrated circuit package having a low profile

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59200427A (ja) * 1983-04-28 1984-11-13 Toshiba Corp ハイブリツド集積回路
JPS59207645A (ja) * 1983-05-11 1984-11-24 Toshiba Corp 半導体装置およびリ−ドフレ−ム
JPS63237373A (ja) * 1987-03-26 1988-10-03 キヤノン株式会社 電気的接続部材及びそれを用いた電気回路部材

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57122592A (en) * 1981-01-23 1982-07-30 Tokyo Shibaura Electric Co Method of producing hybrid integrated circuit
FR2545312B1 (fr) * 1983-04-29 1986-05-30 Thomson Csf Picot de support de fixation de composant electronique sur circuit imprime et support comportant ces picots
US4574879A (en) * 1984-02-29 1986-03-11 The Bergquist Company Mounting pad for solid-state devices
US4626309A (en) * 1984-07-02 1986-12-02 Motorola, Inc. Selective bonding interconnection mask
US4700473A (en) * 1986-01-03 1987-10-20 Motorola Inc. Method of making an ultra high density pad array chip carrier
US4700276A (en) * 1986-01-03 1987-10-13 Motorola Inc. Ultra high density pad array chip carrier
JPS62216259A (ja) * 1986-03-17 1987-09-22 Fujitsu Ltd 混成集積回路の製造方法および構造
JPS62229896A (ja) * 1986-03-29 1987-10-08 株式会社東芝 印刷配線基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59200427A (ja) * 1983-04-28 1984-11-13 Toshiba Corp ハイブリツド集積回路
JPS59207645A (ja) * 1983-05-11 1984-11-24 Toshiba Corp 半導体装置およびリ−ドフレ−ム
JPS63237373A (ja) * 1987-03-26 1988-10-03 キヤノン株式会社 電気的接続部材及びそれを用いた電気回路部材

Also Published As

Publication number Publication date
ATE114213T1 (de) 1994-12-15
EP0471003A1 (en) 1992-02-19
EP0471003B1 (en) 1994-11-17
WO1990013991A1 (en) 1990-11-15
EP0471003A4 (en) 1991-12-06
DE69014202D1 (de) 1994-12-22
JPH04505235A (ja) 1992-09-10
DE69014202T2 (de) 1995-06-01
US5077633A (en) 1991-12-31

Similar Documents

Publication Publication Date Title
JPH0834225B2 (ja) 超高密度パッドアレイ・チップキャリアを接地する方法
US6331679B1 (en) Multi-layer circuit board using anisotropic electro-conductive adhesive layer
JP2981141B2 (ja) グリッドアレイ・プラスチックパッケージ、およびその製造方法、およびその製造に使用されるプラスチック積層体、およびその製造方法
KR101204107B1 (ko) 보편적 풋프린트를 포함하는 반도체 다이 패키지 및 그제조방법
US5717252A (en) Solder-ball connected semiconductor device with a recessed chip mounting area
JP3526788B2 (ja) 半導体装置の製造方法
JPH07283338A (ja) 電子デバイス・パッケージの形成方法
US5896271A (en) Integrated circuit with a chip on dot and a heat sink
CN101872747A (zh) 电子部件模块
EP0871219A3 (en) Metal-based semiconductor circuit substrates
US5559369A (en) Ground plane for plastic encapsulated integrated circuit die packages
JP2808958B2 (ja) 配線基板及びその製造方法
JP3018789B2 (ja) 半導体装置
JP2810130B2 (ja) 半導体パッケージ
US6111308A (en) Ground plane for plastic encapsulated integrated circuit die packages
JP3510841B2 (ja) 板状体、リードフレームおよび半導体装置の製造方法
JP2809316B2 (ja) 電子部品搭載用基板
JP3527589B2 (ja) 半導体装置用パッケージ及びその製造方法
JP2541494B2 (ja) 半導体装置
JP2962575B2 (ja) 半導体装置
JPH03160751A (ja) 半導体装置
JPH09246416A (ja) 半導体装置
US20030205793A1 (en) Wire-bonded chip on board package
WO1995010852A1 (en) Bonding of leads directly over chip active areas
EP1365450A1 (en) An improved wire-bonded chip on board package