DE69014202T2 - Verfahren zur erdung eines chip-trägers mit kontaktfeldern von ultrahoher dichte. - Google Patents

Verfahren zur erdung eines chip-trägers mit kontaktfeldern von ultrahoher dichte.

Info

Publication number
DE69014202T2
DE69014202T2 DE69014202T DE69014202T DE69014202T2 DE 69014202 T2 DE69014202 T2 DE 69014202T2 DE 69014202 T DE69014202 T DE 69014202T DE 69014202 T DE69014202 T DE 69014202T DE 69014202 T2 DE69014202 T2 DE 69014202T2
Authority
DE
Germany
Prior art keywords
chip carrier
earthing
ultra
high density
contact fields
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69014202T
Other languages
English (en)
Other versions
DE69014202D1 (de
Inventor
Bruce Freyman
Barry Miles
Frank Juskey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69014202D1 publication Critical patent/DE69014202D1/de
Publication of DE69014202T2 publication Critical patent/DE69014202T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/838—Bonding techniques
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/156—Material
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    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Wire Bonding (AREA)
DE69014202T 1989-05-01 1990-04-09 Verfahren zur erdung eines chip-trägers mit kontaktfeldern von ultrahoher dichte. Expired - Fee Related DE69014202T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/345,280 US5077633A (en) 1989-05-01 1989-05-01 Grounding an ultra high density pad array chip carrier
PCT/US1990/001828 WO1990013991A1 (en) 1989-05-01 1990-04-09 Method of grounding an ultra high density pad array chip carrier

Publications (2)

Publication Number Publication Date
DE69014202D1 DE69014202D1 (de) 1994-12-22
DE69014202T2 true DE69014202T2 (de) 1995-06-01

Family

ID=23354353

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69014202T Expired - Fee Related DE69014202T2 (de) 1989-05-01 1990-04-09 Verfahren zur erdung eines chip-trägers mit kontaktfeldern von ultrahoher dichte.

Country Status (6)

Country Link
US (1) US5077633A (de)
EP (1) EP0471003B1 (de)
JP (1) JPH0834225B2 (de)
AT (1) ATE114213T1 (de)
DE (1) DE69014202T2 (de)
WO (1) WO1990013991A1 (de)

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US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5175612A (en) * 1989-12-19 1992-12-29 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
KR970011619B1 (ko) * 1990-12-21 1997-07-12 모토로라 인코포레이티드 리드레스 패드 배열 칩 캐리어 패키지 및 그 제조방법
WO1992020097A1 (en) * 1991-04-26 1992-11-12 Citizen Watch Co., Ltd. Semiconductor device and manufacturing method therefor
US5249098A (en) * 1991-08-22 1993-09-28 Lsi Logic Corporation Semiconductor device package with solder bump electrical connections on an external surface of the package
JPH05109922A (ja) * 1991-10-21 1993-04-30 Nec Corp 半導体装置
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5517752A (en) * 1992-05-13 1996-05-21 Fujitsu Limited Method of connecting a pressure-connector terminal of a device with a terminal electrode of a substrate
US5592025A (en) * 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
US5481436A (en) * 1992-12-30 1996-01-02 Interconnect Systems, Inc. Multi-level assemblies and methods for interconnecting integrated circuits
US5479319A (en) * 1992-12-30 1995-12-26 Interconnect Systems, Inc. Multi-level assemblies for interconnecting integrated circuits
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
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ATE114213T1 (de) 1994-12-15
US5077633A (en) 1991-12-31
EP0471003B1 (de) 1994-11-17
JPH0834225B2 (ja) 1996-03-29
DE69014202D1 (de) 1994-12-22
WO1990013991A1 (en) 1990-11-15
JPH04505235A (ja) 1992-09-10
EP0471003A4 (de) 1991-12-06
EP0471003A1 (de) 1992-02-19

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