JPS59200427A - ハイブリツド集積回路 - Google Patents

ハイブリツド集積回路

Info

Publication number
JPS59200427A
JPS59200427A JP7382183A JP7382183A JPS59200427A JP S59200427 A JPS59200427 A JP S59200427A JP 7382183 A JP7382183 A JP 7382183A JP 7382183 A JP7382183 A JP 7382183A JP S59200427 A JPS59200427 A JP S59200427A
Authority
JP
Japan
Prior art keywords
integrated circuit
conductive paste
circuit chip
base body
metallic base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7382183A
Other languages
English (en)
Inventor
Yoshiyuki Suda
良幸 須田
Tamio Saito
斎藤 民雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7382183A priority Critical patent/JPS59200427A/ja
Publication of JPS59200427A publication Critical patent/JPS59200427A/ja
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/27011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 [発明の技術分野] 本発明は、複数個の集積回路チップを備えた・・イブリ
ッド集積回路に関する。
〔発明の技術的背景とその問題点コ 複数個の集積回路チップを回路パターンを有する一個の
基板上に固定し、ワイヤボンディング等で電気的に接続
するハイブリッド集積回路は、例えば大容量のメモリ、
サーマルヘッドの駆動回路部、密着センサ等の光電変換
器の駆動回路部等、多方面で利用されている。
ところで、複数個の集積回路チップを基板tに実装した
場合問題となるのが、接地用の配線であル。例えばサー
マルヘッド等においては、この接地用配線には数10A
程度の電流が流れるたY)、一般の信号伝送路に比べ大
面積の配線パターンを要する。従って接地用配線以外の
配線パターンの占める面積が限られてしまうという問題
点がある。
一方、電子機器の小型化に伴ない、配線パターンの高密
度化が要求されている。しかしながらこのように配線パ
ターンを形成し得る面積が限られているため高密度化に
は限界があっだっまだこのように大面積が接地用配線と
して必要であるため小型化にも限界があった。
[発明の目的] 本発明は以上の点を考慮してなされたもので、高密度の
配線が可能な・・イブリッド集積回路を払。
供することを目的とする。
[発明の概要コ 本発明は、金属基体と、前記金属基体上に形成された絶
縁性樹脂層と、前記絶縁性樹脂層を貫通して前記金属基
体を露出するように形成された孔と、前記孔に充填され
前記金属基体と電気的接続を有する導電性ペーストと、
前記導電性ペーストを介して前記金属基板上に固着され
前記金属基体を接地用配線として用いる回路チップとを
具備したことを特徴とするノ・イブリッド集積回路であ
る。
本発明においては、金属基体としてアルミニウム板、鋼
板等を用いることができる0また絶縁性樹脂としては、
エポキシ樹脂、ポリイミド樹脂、BTレジン等を用いる
ことができる。また導電性ペーストとしてはエポキシ系
Agペースト、エポキシ系Niペースト等の樹脂系導電
性ペースト等を用いることができる。
本発明における絶縁性樹脂層を貫通する孔は、金属基体
上に絶縁性樹脂層をコーティングした後ドリル等の機械
的手段、レーザ光照射等によ多形成することができる。
またスクリーン印刷等の手段によりあらかじめ孔を有す
るパターンの絶縁性樹脂層を形成しても良い。
通常集積回路チップを接着すべき位置のパッドは集積回
路チップの大きさにあわせて、3〜6闘角の大きさに形
成されるため、孔径は製造上の誤差を考慮して0.3〜
1m程度が好ましい。またあまシ孔径が大きすぎると集
積回路チップの固定が不安定と々ってしまう。
また絶縁性樹脂層上には、金箔等の導体箔をラミネート
して所望のパターンにエツチングしだシ導電性ペースト
を印刷したシして回路パターンを形成する。例えば導体
箔を形成する場合、前述の孔の形成は、ラミネートの前
後どちらでも行なうことができる。すなわち導体箔形成
後、導体箔、絶縁性樹脂ともに貫通するように孔を形成
しても良いし、あらかじめ孔を有する絶縁性樹脂層上に
導体箔をラミネートし、孔の部分の導体箔をエツチング
等によシ除去しても良い。
本発明においては、金属基体を接地用配線として用い、
集積回路チップの基板上への固定と、集積回路チップと
接地用配線の電気的接続を導電性ペーストによシ同時に
行なうことができる。
従って絶縁性樹脂層表面に接地用配線を形成する必要が
なくなり、ハイブリッド集積回路を小型にすることがで
きる。一般に金属基板上に絶縁性樹脂層を形成した金属
ベース基板は、熱放散性、熱伝導性の良いことが知られ
ているが、本発明では集積回路チップが絶縁性樹脂に比
べ熱伝導性の良い導電性ペーストを介して直接金属基体
に接続されているため、この集積回路チップからの熱放
散性が非常に良好となる。
まだボンディングワイヤ等による接続に比べ、導電性ペ
ーストによる接続は、接触面積が大きいため流し得る電
流容量も大きく安定性に優れている。さらに導電性ペー
ストによる接−続は電気的に良好であるため、集積回路
チップと接地用配線間における電圧降下を減少すること
ができる。従ってハイブリッド集積回路の消費電力を低
減することができる。また金属基体を接地用配線として
用いることによシ、絶縁性樹脂層上に形成された導体層
に比べ低抵抗であるため外部からのノイズに強く、流し
得る電流容量も大きい。
[発明の効果] 以上説明したように本発明によれば、小型化、高密度化
可能な−・イブリッド集積回路を得ることができる。特
にサーマルヘッドの駆動回路部等の大電流が流れる機器
に用いると効果的である。
[発明の実施例] 本発明の詳細な説明する。
第1図は本実施例を工程順に示す・・イブリッド集積回
路の断面図である。
厚さ1mのステンレス板る金属基体(1)として用い、
この金属基体(1)表面にエポキシ樹脂からなる絶縁性
樹脂層(2)を形成する。次にこの絶縁性樹脂層(2)
表面に金箔(3ンを熱圧着によシラミネートする。
続いてフォトエツチング工程を用い、金箔(3)を所望
形状とし、導体路パターンを形成する(第1図(→)0 次に、孔(4)を形成する。この孔(4)は、数値制御
ボール盤を用い、金箔(3)、絶縁性樹脂層(2)を貫
通して、金属基体(1)が露出するように形成する(第
1図(b))。このとき、金属基体(1)表面を少しけ
ずシとる程度に穴開けを行なうことが好ましい。孔(4
)径は0.5+mとした。このように穴開けを行なうこ
とによシ金属基体(1)表面の酸化物等が除去されるた
め、導電性ペースト(5)との電気的接続が良好となる
このように形成された孔(4)に、導電性ペースト(5
)としてエポキシ系Agペーストを充填し、金属基体(
1)との電気的接続をとる(第1図(C))。続いてと
(7)導電性ペースト(5)上に集積回路チップ(6)
 t 配置し、120℃、加分間ベーキングすることに
ょシ導電性ペースト(5)を固化し、集積回路チップ(
6)を固定する。この導電性ペースト(5)の充填はス
クリーン印刷法、ディスペンサーを用いて行なう。また
この導電性ペースト(5どは、集積回路チップ(6)と
金属基体(1)との電気的接続手段及び基板上への集積
回路チップ(6)の固定手段を兼ねるため、金箔(3)
表面かられずかにもシあがる程度に充填することが好ま
しい。また前記孔(4)も金属基体(1)に凹部を形成
するように設け、この凹部に導電性ペースト(5)を充
填するようにすれば、集積回路チップ(6)の固着の安
定性が増す。集積回路チップ(6)からの配線はボンデ
ィングワイヤ(7)を接続することにより行なう(第1
図(d))。
このように構成されたハイブリッド集積回路では、 ■金属基板を接地用配線として用いることにより大きい
電流容量を得ることが可能であり、また接地電位が安定
しており外部ノイズに対して強固である。
■導電性ペーストを介して直接集積回路チップを金属基
板に固定するため、熱放散性がより一層すぐれたものと
なる。また接地用配線としての金属基板との接続も安定
である。
■孔開けを機械的に行なうことができるため、製造上容
易である。
等の効果を得ることができる。
本実施例では一層の配線であったが、絶縁性樹脂層を導
体箔上に形成し多層配線を行なっても良い。さらに、多
層に配線したのち複数の絶縁性樹脂層を貫通するように
孔開けを行なうことも可能である。また金属基体を集積
回路チップ以外の素子の接地用配線として兼用すること
も可能である。
この場合、孔開け、導電性ペーストの充填を行なって導
体箔と金属基体との電気的導通を図ればよい0
【図面の簡単な説明】
第1図は本発明の詳細な説明するためのハイブリッド集
積回路の断面図。 1・・・金属基体、 2・・・絶縁性樹脂層、 3・・・金箔、 4・・・孔、 5・・・導電性ペースト、 6・・・集積回路チップ、 7・・・ボンディングワイヤ。 代理人 弁理士  則 近 憲 佑 (ほか1名) 第  1  図

Claims (1)

    【特許請求の範囲】
  1. 金属基体と、前記金属基体上に形成された絶縁性樹脂層
    と、前記絶縁性樹脂層を貫通して前記金属基体を露出す
    るように形成された孔と、前記孔に充填され前記金属基
    体と電気的接続を有する導電性ペーストと、前記導電性
    ペーストを介して前記金属基体上に固着され前記金属基
    体を接地用配線として用いる集積回路チップとを具備し
    −こきを特徴とするハイブリッド集積回路。
JP7382183A 1983-04-28 1983-04-28 ハイブリツド集積回路 Pending JPS59200427A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7382183A JPS59200427A (ja) 1983-04-28 1983-04-28 ハイブリツド集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7382183A JPS59200427A (ja) 1983-04-28 1983-04-28 ハイブリツド集積回路

Publications (1)

Publication Number Publication Date
JPS59200427A true JPS59200427A (ja) 1984-11-13

Family

ID=13529196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7382183A Pending JPS59200427A (ja) 1983-04-28 1983-04-28 ハイブリツド集積回路

Country Status (1)

Country Link
JP (1) JPS59200427A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0834225B2 (ja) * 1989-05-01 1996-03-29 モトローラ・インコーポレーテッド 超高密度パッドアレイ・チップキャリアを接地する方法
US6864121B2 (en) * 2000-10-02 2005-03-08 Sanyo Electric Co., Ltd. Method of manufacturing circuit device
JP6163246B1 (ja) * 2016-12-06 2017-07-12 西村陶業株式会社 セラミックス基板の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0834225B2 (ja) * 1989-05-01 1996-03-29 モトローラ・インコーポレーテッド 超高密度パッドアレイ・チップキャリアを接地する方法
US6864121B2 (en) * 2000-10-02 2005-03-08 Sanyo Electric Co., Ltd. Method of manufacturing circuit device
JP6163246B1 (ja) * 2016-12-06 2017-07-12 西村陶業株式会社 セラミックス基板の製造方法
JP2018093100A (ja) * 2016-12-06 2018-06-14 西村陶業株式会社 セラミックス基板の製造方法

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