JPH08236534A - Formation of passivation film for semiconductor element - Google Patents

Formation of passivation film for semiconductor element

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Publication number
JPH08236534A
JPH08236534A JP4146895A JP4146895A JPH08236534A JP H08236534 A JPH08236534 A JP H08236534A JP 4146895 A JP4146895 A JP 4146895A JP 4146895 A JP4146895 A JP 4146895A JP H08236534 A JPH08236534 A JP H08236534A
Authority
JP
Japan
Prior art keywords
nitride film
wiring
film
forming
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4146895A
Other languages
Japanese (ja)
Inventor
Daiichi Harada
大一 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP4146895A priority Critical patent/JPH08236534A/en
Publication of JPH08236534A publication Critical patent/JPH08236534A/en
Withdrawn legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: To inhibit the generation of hillocks on uppermost Al wiring layers and also conduct efficiently the recovery of a device from damage to the device by a method wherein after the uppermost Al wiring layers are formed, a direct single-wafer type plasma nitride film is formed without performing an H2 sintering treatment and thereafter, an annealing is performed. CONSTITUTION: Uppermost Al wiring layers 12 are formed and thereafter, a direct single-wafer type plasma nitride film 13 is formed on the gas condition of SiH4 gas of 12 to 22cc/1, NH3 gas of 10 to 15cc/1 and N2 gas of 420 to 850cc/1 without performing an H2 sintering treatment and thereafter, an annealing is performed. For example, the layers 12 are formed on a semiconductor substrate 11 formed with an element, such as a transistor. Then, a direct single-wafer type plasma nitride film 13 is formed on a prescribed gas condition without performing an H2 sintering treatment. After that, a passivation annealing is performed and a passivation process ends. Thereby, the amount of heat, which is applied to the wiring layers 12, is suppressed low and the generation of hillocks on the wiring layers 12 can be suppressed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子のパッシベ
ーション膜の形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a passivation film of a semiconductor device.

【0002】[0002]

【従来の技術】従来のこのような分野の技術としては、
例えば、以下に示すようなものがあった。図2はかかる
従来の半導体素子の製造工程断面図である。 (1)まず、図2(a)に示すように、トランジスタ等
の素子を形成した半導体基板1上に最上層Al配線2を
形成後、素子のダメージの回復を図るために、H2 シン
ター(400℃×30分)を行う。
2. Description of the Related Art Conventional techniques in this field include:
For example, there were the following. FIG. 2 is a cross-sectional view of the manufacturing process of such a conventional semiconductor device. (1) First, as shown in FIG. 2A, after forming an uppermost Al wiring 2 on a semiconductor substrate 1 on which elements such as transistors are formed, an H 2 sintering ( 400 ° C. × 30 minutes).

【0003】(2)次に、図2(b)に示すように、常
圧のPSG膜3を形成する。 (3)次に、図2(c)に示すように、バッチ式プラズ
マ窒化膜(PE−SiN)4を形成する。ここで、プラ
ズマ窒化膜4は耐湿性を向上させるため、PSG膜3は
プラズマ窒化膜4のストレスを緩和させるために形成し
ている。 (4)最後に、図2(d)に示すように、パッシベーシ
ョンアニール(350℃〜400℃×30分)を行い、
再び、素子のダメージの回復を行う。
(2) Next, as shown in FIG. 2B, the PSG film 3 at normal pressure is formed. (3) Next, as shown in FIG. 2C, a batch type plasma nitride film (PE-SiN) 4 is formed. Here, the plasma nitride film 4 is formed to improve the moisture resistance, and the PSG film 3 is formed to relieve the stress of the plasma nitride film 4. (4) Finally, as shown in FIG. 2D, passivation annealing (350 ° C. to 400 ° C. × 30 minutes) is performed,
Again, the damage of the element is recovered.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、以上述
べた従来の半導体素子の製造方法では、H2 シンター処
理を行った際に、Al配線2中にヒロック5と呼ばれる
突起物が現れ、ひどい場合には、隣接Al配線とショー
トしてしまうという問題点があった。本発明は、上記問
題点を除去し、最上層Al配線のヒロックの発生を抑制
するとともに、デバイスのダメージの回復も効率的に行
うことができ、信頼性の高いショートのないデバイスが
作製可能となる半導体素子のパッシベーション膜の形成
方法を提供することを目的とする。
However, in the conventional method for manufacturing a semiconductor element described above, when H 2 sintering is performed, a protrusion called a hillock 5 appears in the Al wiring 2 and is severe. Had a problem of short-circuiting with the adjacent Al wiring. INDUSTRIAL APPLICABILITY The present invention eliminates the above-mentioned problems, suppresses the occurrence of hillocks in the uppermost Al wiring, and efficiently recovers the damage to the device, so that a highly reliable device without short circuit can be manufactured. It is an object of the present invention to provide a method for forming a passivation film for a semiconductor element.

【0005】[0005]

【課題を解決するための手段】本発明は、上記目的を達
成するために、 (A)半導体素子のパッシベーション膜の形成方法にお
いて、最上層Al配線(12)を形成後に、H2 シンタ
ー処理を行うことなく、直接枚葉式プラズマ窒化膜(1
3)を形成し、その後にアニールを行うようにしたもの
である。
In order to achieve the above object, the present invention provides (A) a method of forming a passivation film of a semiconductor device, which comprises performing a H 2 sintering process after forming an uppermost Al wiring (12). Without directly performing single-wafer plasma nitride film (1
3) is formed and then annealing is performed.

【0006】(B)半導体素子のパッシベーション膜の
形成方法において、最上層Al配線(22)を形成後
に、H2 シンター処理を行うことなく、枚葉式プラズマ
酸化膜(23)を形成し、その後にSOG(24)を塗
布し、続いて枚葉式、バッチ式いずれかのプラズマ窒化
膜(25)を形成し、アニールを行うようにしたもので
ある。
(B) In the method for forming a passivation film of a semiconductor device, after forming the uppermost Al wiring (22), a single wafer type plasma oxide film (23) is formed without performing H 2 sintering treatment, and thereafter, Is coated with SOG (24), and subsequently, a single-wafer type or a batch type plasma nitride film (25) is formed and annealed.

【0007】(C)上記(B)記載の半導体素子のパッ
シベーション膜の形成方法において、前記枚葉式プラズ
マ酸化膜(23)は、屈折率1.49〜1.55であ
る。
(C) In the method of forming a passivation film for a semiconductor device according to (B), the single-wafer plasma oxide film (23) has a refractive index of 1.49 to 1.55.

【0008】[0008]

【作用】[Action]

(1)請求項1記載の半導体素子のパッシベーション膜
の形成方法によれば、Al配線形成後、H2 シンター処
理を行わずに、枚葉式プラズマ窒化膜を直接形成するよ
うにしているために、Al配線に加わる熱量が低く押さ
えられ、ヒロックの発生を抑制することができる。
(1) According to the method for forming a passivation film for a semiconductor device according to claim 1, the single-wafer plasma nitride film is directly formed after the Al wiring is formed without performing the H 2 sintering process. , The amount of heat applied to the Al wiring is suppressed to a low level, and the occurrence of hillocks can be suppressed.

【0009】また、プラズマ窒化膜の生成条件を、N−
H結合が多い条件で生成しているために、パッシベーシ
ョンアニール時に、H2 が多く発生し、デバイスのダメ
ージの回復も効率的に行うことができる。 (2)請求項2記載の半導体素子のパッシベーション膜
の形成方法によれば、Al配線形成後、H2 シンター処
理を行わずに、枚葉式プラズマ酸化膜を形成するように
しているために、Al配線に加わる熱量が低く押さえら
れ、ヒロックの発生を抑制することができる。
The plasma nitride film formation conditions are N-
Since H bonds are generated under the condition that many H bonds are generated, a large amount of H 2 is generated during the passivation annealing, and the damage of the device can be efficiently recovered. (2) According to the method for forming a passivation film of a semiconductor device according to claim 2, the single-wafer plasma oxide film is formed without performing the H 2 sintering process after forming the Al wiring. The amount of heat applied to the Al wiring can be suppressed to a low level, and hillock generation can be suppressed.

【0010】その後、SOGを塗布し、次いで、枚葉式
あるいはバッチ式プラズマ窒化膜を生成し、その後にア
ニールを行っているために、SOGから脱離したH2
が、プラズマ酸化膜を通過する際にH2 に変換されるた
めに、効率的にデバイスのダメージの回復を行うことが
できる。さらに、プラズマ酸化膜によりヒロックの成長
は押さえられ、配線のショートのない信頼性の高いデバ
イスが作製できる。
After that, SOG is applied, then a single-wafer or batch-type plasma nitride film is formed, and annealing is performed thereafter. Therefore, H 2 O desorbed from SOG is formed.
However, since it is converted into H 2 when passing through the plasma oxide film, the damage of the device can be efficiently recovered. Furthermore, the growth of hillocks is suppressed by the plasma oxide film, and a highly reliable device without a short circuit of wiring can be manufactured.

【0011】また、前記枚葉式プラズマ酸化膜は、屈折
率1.49〜1.55としたので、SOGから脱離した
2 Oを効率的にH2 に変換することができる。因み
に、屈折率1.45になると、SOGから脱離したH2
Oは前記枚葉式プラズマ酸化膜をそのまま透過すること
になり不具合である。
Further, since the single-wafer plasma oxide film has a refractive index of 1.49 to 1.55, H 2 O desorbed from SOG can be efficiently converted into H 2 . By the way, when the refractive index becomes 1.45, H 2 desorbed from SOG
O penetrates the single-wafer plasma oxide film as it is, which is a problem.

【0012】[0012]

【実施例】以下、本発明の実施例について図を参照しな
がら順次説明する。図1は本発明の第1実施例を示す半
導体素子の製造工程断面図である。 (1)まず、図1(a)に示すように、トランジスタ等
の素子を形成した半導体基板11上に最上層Al配線1
2を形成する。
Embodiments of the present invention will be sequentially described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device manufacturing process showing a first embodiment of the present invention. (1) First, as shown in FIG. 1A, the uppermost Al wiring 1 is formed on a semiconductor substrate 11 on which elements such as transistors are formed.
Form 2

【0013】(2)次に、図1(b)に示すように、最
上層Al配線12を形成後、H2 シンター処理をせず
に、直接枚葉式プラズマ窒化膜13を形成する。 (3)次に、図1(c)に示すように、その後、パッシ
ベーションアニールを施し、パッシベーション工程を終
了する。この時、枚葉式プラズマ窒化膜の生成条件は、
SiH4 流量を12〜22cc/lと低く押さえ、NH
3 は10〜15cc/l、N2 は400〜850cc/
lとする。これによりプラズマ窒化膜はN−H結合が大
きくなり、アニール時に多くのH2 の脱離が見られ、デ
バイスのダメージからの回復を効率的に行うことが可能
となる。これにより、H2 シンター処理を省いた分を補
うことが可能となる。
(2) Next, as shown in FIG. 1B, after forming the uppermost Al wiring 12, the single-wafer plasma nitride film 13 is directly formed without H 2 sintering treatment. (3) Next, as shown in FIG. 1C, thereafter, passivation annealing is performed to complete the passivation process. At this time, the conditions for forming the single-wafer plasma nitride film are:
SiH 4 flow rate as low as 12-22 cc / l, NH
3 is 10 to 15 cc / l, N 2 is 400 to 850 cc / l
Let l. As a result, the plasma nitride film has a large N—H bond, a large amount of H 2 is desorbed during annealing, and the device can be efficiently recovered from damage. This makes it possible to compensate for the elimination of the H 2 sintering process.

【0014】図3は本発明の第2実施例を示す半導体素
子の製造工程断面図である。 (1)まず、図3(a)に示すように、トランジスタ等
の素子を形成した半導体基板21上に最上層Al配線2
2を形成する。 (2)次に、図3(b)に示すように、枚葉式プラズマ
酸化膜23を約1000〜3000Å形成する。
FIG. 3 is a sectional view of a semiconductor device manufacturing process showing the second embodiment of the present invention. (1) First, as shown in FIG. 3A, the uppermost Al wiring 2 is formed on a semiconductor substrate 21 on which elements such as transistors are formed.
Form 2 (2) Next, as shown in FIG. 3B, a single-wafer plasma oxide film 23 is formed in a thickness of about 1000 to 3000 liters.

【0015】(3)次に、図3(c)に示すように、S
OG24を回転法により形成する。 (4)続いて、図3(d)に示すように、枚葉式、バッ
チ式のいずれかにより、プラズマ窒化膜25を形成す
る。 (5)最後に、図3(e)に示すように、パッシベーシ
ョンアニールを行う。枚葉式プラズマ酸化膜の生成条件
としては、圧力は1.8〜2.2Torr、SiH4
6.5〜11.0cc/l、N2 Oは170〜260c
c/lとし、屈折率1.49〜1.55の膜を作製し、
使用する。
(3) Next, as shown in FIG.
The OG 24 is formed by the rotation method. (4) Subsequently, as shown in FIG. 3D, the plasma nitride film 25 is formed by either a single wafer method or a batch method. (5) Finally, as shown in FIG. 3E, passivation annealing is performed. As the conditions for producing the single-wafer plasma oxide film, the pressure is 1.8 to 2.2 Torr, SiH 4 is 6.5 to 11.0 cc / l, and N 2 O is 170 to 260 c.
c / l, a film having a refractive index of 1.49 to 1.55 was prepared,
use.

【0016】ここで、枚葉式プラズマ酸化膜は、屈折率
1.49〜1.55としたので、SOGから脱離したH
2 Oを効率的にH2 に変換することができる。例えば、
屈折率1.45になると、SOGから脱離したH2 Oは
プラズマ酸化膜をそのまま透過することになり不具合で
ある。なお、本発明は、上記実施例に限定されるもので
はなく、本発明の趣旨に基づき種々の変形が可能であ
り、それらを本発明の範囲から排除するものではない。
Since the single-wafer plasma oxide film has a refractive index of 1.49 to 1.55, H desorbed from SOG is used.
2 O can be efficiently converted to H 2 . For example,
When the refractive index is 1.45, H 2 O desorbed from SOG directly passes through the plasma oxide film, which is a problem. The present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

【0017】[0017]

【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 (1)請求項1記載の発明によれば、半導体素子のパッ
シベーション膜の形成工程において、Al配線パターン
形成後、H2 シンター処理を行わずに、枚葉式プラズマ
窒化膜を直接形成するようにしているために、Al配線
に加わる熱量が低く押さえられ、ヒロックの発生を抑制
することができる。
As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the invention of claim 1, in the step of forming the passivation film of the semiconductor element, after the Al wiring pattern is formed, the single-wafer plasma nitride film is directly formed without performing the H 2 sintering process. Therefore, the amount of heat applied to the Al wiring can be suppressed low, and the generation of hillocks can be suppressed.

【0018】また、プラズマ窒化膜の生成条件を、N−
H結合が多い条件で生成しているために、パッシベーシ
ョンアニール時にH2 が多く発生し、デバイスのダメー
ジの回復も効率的に行うことができ、信頼性の高いショ
ートのないデバイスが作製可能となる。 (2)請求項2記載の発明によれば、Al配線形成後、
2 シンター処理を行わずに、枚葉式プラズマ酸化膜を
形成するようにしているために、Al配線に加わる熱量
が低く押さえられ、ヒロックの発生を抑制することが可
能となる。
The plasma nitride film formation conditions are N-
Since the H-bonds are generated under a large number of conditions, a large amount of H 2 is generated during the passivation anneal, the damage to the device can be efficiently recovered, and a highly reliable device without a short circuit can be manufactured. . (2) According to the invention of claim 2, after the Al wiring is formed,
Since the single-wafer plasma oxide film is formed without performing the H 2 sintering process, the amount of heat applied to the Al wiring can be suppressed to a low level, and the generation of hillocks can be suppressed.

【0019】その後、SOGを塗布し、次いで、枚葉式
あるいはバッチ式プラズマ窒化膜を生成し、その後にア
ニールを行っているために、SOGから脱離したH2
が、プラズマ酸化膜を通過する際にH2 に変換されるた
めに、効率的にデバイスのダメージの回復を行うことが
可能となる。さらに、プラズマ酸化膜によりヒロックの
成長は押さえられ、配線のショートのない信頼性の高い
デバイスが作成可能となる。
After that, SOG is applied, then a single-wafer or batch-type plasma nitride film is formed, and annealing is performed thereafter. Therefore, H 2 O desorbed from SOG is formed.
However, since it is converted into H 2 when passing through the plasma oxide film, it is possible to efficiently recover the damage to the device. Furthermore, the growth of hillocks is suppressed by the plasma oxide film, and a highly reliable device without wiring short circuit can be manufactured.

【0020】さらなる効果としては、配線幅が狭くなる
に従い、プラズマ窒化膜のカバレッジが悪くなり、デバ
イスの耐湿性が劣化するという問題に対しても、SOG
を塗布することにより、プラズマ窒化膜のカバレッジ及
び耐湿性が大幅に改善される。また、前記枚葉式プラズ
マ酸化膜は、屈折率1.49〜1.55としたので、S
OGから脱離したH2 Oを効率的にH2 に変換すること
ができる。
As a further effect, as the wiring width becomes narrower, the coverage of the plasma nitride film deteriorates, and the moisture resistance of the device deteriorates.
By coating, the coverage and moisture resistance of the plasma nitride film are significantly improved. Since the single-wafer plasma oxide film has a refractive index of 1.49 to 1.55, S
H 2 O desorbed from OG can be efficiently converted to H 2 .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例を示す半導体素子の製造工
程断面図である。
FIG. 1 is a sectional view of a semiconductor device in a manufacturing process showing a first embodiment of the present invention.

【図2】従来の半導体素子の製造工程断面図である。FIG. 2 is a cross-sectional view of a conventional semiconductor device manufacturing process.

【図3】本発明の第2実施例を示す半導体素子の製造工
程断面図である。
FIG. 3 is a sectional view of a semiconductor device in the manufacturing process showing the second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11,21 半導体基板 12,22 最上層Al配線 13 枚葉式プラズマ窒化膜 23 枚葉式プラズマ酸化膜 24 SOG 25 プラズマ窒化膜(枚葉式又はバッチ式) 11, 21 Semiconductor substrate 12, 22 Top layer Al wiring 13 Single wafer type plasma nitride film 23 Single wafer type plasma oxide film 24 SOG 25 Plasma nitride film (single wafer type or batch type)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 最上層Al配線を形成後に、H2 シンタ
ー処理を行うことなく、直接枚葉式プラズマ窒化膜をS
iH4 12〜22cc/l、NH3 10〜15cc/
l、N2 420〜850cc/lのガス条件で形成し、
その後にアニールをすることを特徴とする半導体素子の
パッシベーション膜の形成方法。
1. A single-wafer plasma nitride film is directly subjected to S treatment without performing H 2 sintering after forming the uppermost Al wiring.
iH 4 12-22 cc / l, NH 3 10-15 cc /
1, N 2 420 to 850 cc / l under gas conditions,
A method for forming a passivation film of a semiconductor device, characterized by performing annealing thereafter.
【請求項2】 最上層Al配線を形成後に、H2 シンタ
ー処理を行うことなく、枚葉式プラズマ酸化膜を圧力
1.8〜22Torr、SiH4 6.5〜11cc/
l、N2 O170〜260cc/lのガス条件で屈折率
1.49〜1.55の膜を形成し、その後にSOGを塗
布し、続いて枚葉式、バッチ式いずれかのプラズマ窒化
膜を形成し、アニールすることを特徴とする半導体素子
のパッシベーション膜の形成方法。
2. A single-wafer plasma oxide film having a pressure of 1.8 to 22 Torr and SiH 4 6.5 to 11 cc / without H 2 sintering treatment after forming the uppermost Al wiring.
l, N 2 O 170-260 cc / l gas conditions to form a film having a refractive index of 1.49-1.55, and then SOG is applied, followed by a single-wafer type or batch type plasma nitride film. A method of forming a passivation film for a semiconductor device, which comprises forming and annealing.
JP4146895A 1995-03-01 1995-03-01 Formation of passivation film for semiconductor element Withdrawn JPH08236534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4146895A JPH08236534A (en) 1995-03-01 1995-03-01 Formation of passivation film for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4146895A JPH08236534A (en) 1995-03-01 1995-03-01 Formation of passivation film for semiconductor element

Publications (1)

Publication Number Publication Date
JPH08236534A true JPH08236534A (en) 1996-09-13

Family

ID=12609211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4146895A Withdrawn JPH08236534A (en) 1995-03-01 1995-03-01 Formation of passivation film for semiconductor element

Country Status (1)

Country Link
JP (1) JPH08236534A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345319A (en) * 2000-05-31 2001-12-14 Fuji Electric Co Ltd Method of manufacturing semiconductor device
US9786717B2 (en) 2015-04-22 2017-10-10 Canon Kabushiki Kaisha Method of manufacturing photoelectric conversion device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345319A (en) * 2000-05-31 2001-12-14 Fuji Electric Co Ltd Method of manufacturing semiconductor device
US9786717B2 (en) 2015-04-22 2017-10-10 Canon Kabushiki Kaisha Method of manufacturing photoelectric conversion device

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