JPH10163206A - Formation of wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent generation of exfoliation at the interface of a poly Si layer and a silicide layer when a silicon oxide film for flattening which covers a laminate formed by stacking the silicide layer on the poly Si layer is heattreated in an oxidizing atmosphere. SOLUTION: MOS type transistors T1 , T2 are formed on the surface of a semiconductor substrate 10. Each of the transistors has a gate electrode composed of a laminate formed by stacking a silicide layer 14b of WSi or the like on a poly Si layer 14a. After an insulating film 16 for surface protection is formed on the substrate surface by a CVD method and covers the gate electrode, a silicon oxide film 18 for flattening is formed by an SOG coating method or a flattening CVD method. After a gate electrode is subjected to high speed annealing in an inert gas atmosphere, and the coupling of the poly Si layer and the silicide layer is increased, the film 18 is heat-treated in an oxidizing atmosphere, and the film quality is made dense. After that, a wiring layer is formed on the film 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS type LSI.
In particular, the present invention relates to a wiring formation method suitable for use in forming a wiring of a semiconductor device, particularly to a flattening silicon oxide film covering a stack of a poly-Si (silicon) layer and a silicide layer before heat treatment in an oxidizing atmosphere. RTA (Rapid
Thermal annealing (rapid thermal annealing)) prevents the interface between the poly-Si layer and the silicide layer from being peeled off during the heat treatment.

[0002]

2. Description of the Related Art Conventionally, as a wiring forming method using a silicon oxide film for flattening, a method shown in FIG. 7 has been known (for example, see Japanese Patent Application Laid-Open No. 7-37879).

In the process of FIG. 7, a plurality of MOS transistors T are formed on the surface of the semiconductor substrate 1 by a known method. Reference numeral 2 denotes a gate insulating film made of silicon oxide, and reference numeral 3 denotes a poly-Si (silicon) layer as a gate electrode. The illustration of the source and drain regions is omitted for simplicity.

Next, a silicon oxide film 4 is formed on the surface of the substrate by a CVD (chemical vapor deposition) method so as to cover a step-forming material such as a poly-Si layer 3. Then, SOG (spin-on-glass) is formed on the silicon oxide film 4.
After the solution is spin-coated to form a coating film in a flat shape, the coating film is formed at 650 ° C.3 in a mixed gas atmosphere of steam and oxygen.
By performing a heat treatment for 0 minutes, a flat silicon oxide film 5 having dense film quality is obtained. Thereafter, a desired wiring layer is formed on the silicon oxide film 5.

[0005]

According to the above-mentioned conventional method, as shown in FIG. 8, a poly-Si layer 3a is used as a gate electrode.
It has been found that, when a laminate (so-called polycide layer) in which a silicide layer 3b made of WSi or the like is stacked on the substrate is used, peeling occurs at the interface between the polySi layer 3a and the silicide layer 3b during heat treatment in an oxidizing atmosphere. . Such peeling reduces the reliability of the electrode or wiring made of the polycide layer. Note that P ₁ and P ₂ in FIG. 8 indicate side spacers, and other symbols indicate the same parts as in FIG.

An object of the present invention is to provide a novel wiring forming method capable of preventing peeling at a lamination interface.

[0007]

According to the present invention, there is provided a method of forming a wiring, comprising the steps of: forming a laminate in which a silicide layer is superimposed on a polysilicon layer on one principal surface of a substrate; Forming an insulating film for surface protection covering the insulating film, forming a silicon oxide film for planarization on the insulating film, and subjecting the stack to a rapid thermal annealing treatment in an inert gas atmosphere. Strengthening the bond between the polysilicon layer and the silicide layer; heat treating the silicon oxide film in an oxidizing atmosphere after the rapid thermal annealing to densify the film; Forming a wiring layer on the silicon oxide film.

According to the method of the present invention, before the heat treatment in the oxidizing atmosphere, the bonding between the poly-Si layer and the silicide layer is strengthened by the RTA treatment in the inert gas atmosphere. Peeling at the interface between these layers can be prevented.

[0009]

1 to 6 show a wiring forming method according to an embodiment of the present invention. Steps (1) to (6) corresponding to the respective drawings will be sequentially described.

(1) A plurality of MOS transistors T ₁ and T ₂ are formed on the surface of a semiconductor substrate 10 made of, for example, silicon by a known method such as a silicon gate process. The transistor T _1, 12 denotes a gate insulating film made of silicon oxide or the like. On the insulating film 12, a stack is formed in which a silicide layer 14b is stacked on a poly-Si layer 14a as a gate electrode, and side spacers Q ₁ and Q ₂ made of silicon oxide or the like are formed on both sides of the stack. As an example, the poly-Si layer 14a is made of phosphorus-doped poly-Si, and the silicide layer 14b is made of WSi (tungsten silicide). Side spacer Q ₁ ,
_On the substrate surface below Q ₂ , N ⁻ -type source and drain regions are formed, respectively, and side spacers Q are formed.
N ⁺ -type source and drain regions S and D are formed on the substrate surface on both sides of ₁ and Q ₂ , respectively, so as to be continuous with the N ⁻ -type source and drain regions. Transistor T ₂ are, it has the same configuration as that of the transistor T _1.

(2) The transistors T ₁ and T _{2 are} formed on the substrate surface.
Then, an insulating film 16 for protecting the surface is formed by a CVD method so as to cover the step forming material such as the gate electrode. As the insulating film 16, a BPSG (boron-phosphosilicate glass) film or a PS
A G (phosphosilicate glass) film can be formed. B
When the PSG film is formed by the normal pressure CVD method, the formation conditions are: substrate temperature: 400 ° C. source gas: SiH ₄ (46.25 sccm) + PH ₃ (8.75 sccm) + B ₂ H ₆ (7.5 sccm) + O ₂ ( 7000 sccm) + N ₂ (50000 sccm).

When the PSG film is formed by the normal pressure CVD method, the forming conditions are as follows: substrate temperature: 400 ° C. source gas: SiH ₄ (240 sccm) + PH ₃ (70 sccm) + N ₂ O (5000 sccm) + N ₂ (2730 sccm) It can be.

(3) A silicon oxide film 18 for planarization is formed on the insulating film 16. For this purpose, the following method can be used as an example. That is, a solution in which hydrogen silsesquioxane resin (HSi _3/2 ) _n is dissolved in MIBK (methyl isobutyl ketone) is flatly applied to the upper surface of the substrate by a spin coating method. The application conditions at this time are as follows: rotation speed: 5000 rpm, rotation application time: 30 seconds, coating film thickness: about 300 nm.

Next, the coating film is subjected to a low-temperature annealing treatment at 400 ° C. or lower. This low-temperature annealing treatment is for removing the solvent and causing a glass transition, and can be performed under the following conditions as an example. That is,
After hot plate baking at 150 ° C. for 60 seconds + 200 ° C. for 60 seconds + 300 ° C. for 60 seconds in an inert gas atmosphere, annealing is performed at 400 ° C. for 60 minutes in an inert gas atmosphere in a vertical furnace. As a result, the coating film becomes a preceramic silicon oxide film (which is insoluble in an organic solvent but does not proceed sufficiently in crosslinking) 18.

(4) The gate electrodes of the transistors T ₁ and T ₂ are subjected to an RTA process in an inert gas atmosphere. When a lamp annealing process is used as the RTA process, the processing conditions can be set as follows: gas atmosphere: N ₂ 850 to 1000 ° C., temperature rise time: 10 seconds, 850 to 1000 ° C. maintenance time: 10 seconds. As a result, the reaction is promoted at the interface between the poly-Si layer 14a and the silicide layer 14b, and the bonding between the layers 14a and 14b is strengthened.

(5) The silicon oxide film 18 is subjected to a high-temperature heat treatment in an oxidizing atmosphere. As an example, when heat treatment is performed in an atmosphere of a combustion gas of H ₂ and O ₂ (mixed gas of steam and oxygen), the processing conditions are as follows: gas flow rate: H ₂ = 10 slm O ₂ = 6.67 slm temperature: 700 to 800 ° C. Time: 10 minutes. As a result, the silicon oxide film 18
Becomes a ceramic-like dense film quality.

(6) A wiring material such as an Al alloy is deposited on the silicon oxide film 18, and the deposited layer is patterned to form desired wiring layers 20a to 20c.

According to the above-described embodiment, prior to the high-temperature heat treatment, the bonding between the poly-Si layer 14a and the silicide layer 14b is strengthened by subjecting the gate electrode to RTA treatment in an inert gas atmosphere in the step of FIG. Therefore, no peeling was observed at the interface between the layers 14a and 14b even when the heat treatment was performed in the step of FIG.

The present invention is not limited to the embodiment described above, but can be implemented in various modified forms. For example, the following changes are possible.

(1) The material for forming the silicon oxide film 18 is not limited to hydrogen silsesquioxane resin, but may be organic SO.
G or inorganic SOG may be used. Further, the silicon oxide film 18 is not limited to the coating method, and may be formed by a flattening CVD method (for example, using TEOS and O ₃ as source gases).

(2) The oxidizing atmosphere for the heat treatment after the RTA treatment is not limited to the combustion gas of H ₂ and O ₂ , but may be a mixed gas of a combustion gas and an inert gas, water vapor, or a mixed gas of a water vapor and an inert gas. Alternatively, dry oxygen, a mixed gas of dry oxygen and an inert gas, or the like may be used.

[0022]

As described above, according to the present invention, by performing the RTA process before the heat treatment, it is possible to prevent peeling at the interface of the silicide / poly-Si lamination during the heat treatment. The effect of greatly improving the reliability of the electrodes or wirings formed by lamination is obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a substrate showing a transistor forming step in a wiring forming method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a substrate showing an insulating film forming step following the step of FIG. 1;

FIG. 3 is a cross-sectional view of a substrate showing a step of forming a silicon oxide film subsequent to the step of FIG. 2;

FIG. 4 is a cross-sectional view of the substrate showing an RTA processing step following the step of FIG. 3;

FIG. 5 is a cross-sectional view of the substrate showing a heat treatment step following the step of FIG. 4;

6 is a cross-sectional view of the substrate showing a wiring forming step following the step of FIG. 5;

FIG. 7 is a sectional view of a substrate for explaining a conventional wiring forming method.

FIG. 8 is a cross-sectional view of a substrate showing a polycide gate structure.

[Explanation of symbols]

10: semiconductor substrate, 12: gate insulating film, 14a: poly-Si layer, 14b: silicide layer, 16: insulating film, 18:
Silicon oxide film, 20a to 20c: wiring layer.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/336 H01L 29/78 301P

Claims (1)

[Claims] A step of forming, on one main surface of a substrate, a laminate in which a silicide layer is superimposed on a polysilicon layer; and a step of forming an insulating film for surface protection over the one main surface by covering the laminate. Forming a silicon oxide film for planarization on the insulating film; and performing high-speed thermal annealing on the stack in an inert gas atmosphere to strengthen the bond between the polysilicon layer and the silicide layer. Performing a heat treatment in an oxidizing atmosphere on the silicon oxide film after the rapid thermal annealing treatment to densify the film quality; and forming a wiring layer on the silicon oxide film after the heat treatment. And a wiring forming method including: